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8287926: AArch64: intrinsics for divideUnsigned and remainderUnsigned methods in java.lang.Integer and java.lang.Long

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Reviewed-by: adinn, ngasson
This commit is contained in:
Andrew Haley 2022-06-13 14:35:43 +00:00
parent 33ed0365c3
commit 0207d761f4
1 changed files with 66 additions and 2 deletions
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68
src/hotspot/cpu/aarch64/aarch64.ad
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@ -11356,7 +11356,7 @@ instruct modI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
ins_cost(INSN_COST * 22);
format %{ "sdivw rscratch1, $src1, $src2\n\t"
"msubw($dst, rscratch1, $src2, $src1" %}
"msubw $dst, rscratch1, $src2, $src1" %}
ins_encode(aarch64_enc_modw(dst, src1, src2));
ins_pipe(idiv_reg_reg);
@ -11369,12 +11369,76 @@ instruct modL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
ins_cost(INSN_COST * 38);
format %{ "sdiv rscratch1, $src1, $src2\n"
"msub($dst, rscratch1, $src2, $src1" %}
"msub $dst, rscratch1, $src2, $src1" %}
ins_encode(aarch64_enc_mod(dst, src1, src2));
ins_pipe(ldiv_reg_reg);
%}
// Unsigned Integer Divide
instruct UdivI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
match(Set dst (UDivI src1 src2));
ins_cost(INSN_COST * 19);
format %{ "udivw $dst, $src1, $src2" %}
ins_encode %{
__ udivw($dst$$Register, $src1$$Register, $src2$$Register);
%}
ins_pipe(idiv_reg_reg);
%}
// Unsigned Long Divide
instruct UdivL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
match(Set dst (UDivL src1 src2));
ins_cost(INSN_COST * 35);
format %{ "udiv $dst, $src1, $src2" %}
ins_encode %{
__ udiv($dst$$Register, $src1$$Register, $src2$$Register);
%}
ins_pipe(ldiv_reg_reg);
%}
// Unsigned Integer Remainder
instruct UmodI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
match(Set dst (UModI src1 src2));
ins_cost(INSN_COST * 22);
format %{ "udivw rscratch1, $src1, $src2\n\t"
"msubw $dst, rscratch1, $src2, $src1" %}
ins_encode %{
__ udivw(rscratch1, $src1$$Register, $src2$$Register);
__ msubw($dst$$Register, rscratch1, $src2$$Register, $src1$$Register);
%}
ins_pipe(idiv_reg_reg);
%}
// Unsigned Long Remainder
instruct UModL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
match(Set dst (UModL src1 src2));
ins_cost(INSN_COST * 38);
format %{ "udiv rscratch1, $src1, $src2\n"
"msub $dst, rscratch1, $src2, $src1" %}
ins_encode %{
__ udiv(rscratch1, $src1$$Register, $src2$$Register);
__ msub($dst$$Register, rscratch1, $src2$$Register, $src1$$Register);
%}
ins_pipe(ldiv_reg_reg);
%}
// Integer Shifts
// Shift Left Register