Merge
This commit is contained in:
Prasanta Sadhukhan
commit
046262a0f5
2
.hgtags
2
.hgtags
@ -520,3 +520,5 @@ f0f5d23449d31f1b3580c8a73313918cafeaefd7 jdk-12+11
|
||||
f8626bcc169813a4b2a15880386b952719d1d6d1 jdk-12+15
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||||
199658d1ef860cdc17055b4fd3e94b057f292fe9 jdk-12+16
|
||||
eefa65e142af305923d2adcd596fab9c639723a1 jdk-12+17
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||||
e38473506688e0995e701fc7f77d5a91b438ef93 jdk-12+18
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||||
dc1f9dec2018a37fedba47d8a2aedef99faaec64 jdk-12+19
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||||
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@ -62,9 +62,8 @@ $ make exploded-test TEST=tier2</code></pre>
|
||||
<p>If you want, you can single out an individual test or a group of tests, for instance <code>gtest:LogDecorations</code> or <code>gtest:LogDecorations.level_test_vm</code>. This can be particularly useful if you want to run a shaky test repeatedly.</p>
|
||||
<p>For Gtest, there is a separate test suite for each JVM variant. The JVM variant is defined by adding <code>/<variant></code> to the test descriptor, e.g. <code>gtest:Log/client</code>. If you specify no variant, gtest will run once for each JVM variant present (e.g. server, client). So if you only have the server JVM present, then <code>gtest:all</code> will be equivalent to <code>gtest:all/server</code>.</p>
|
||||
<h3 id="special-tests">Special tests</h3>
|
||||
<p>A handful of odd tests that are not covered by any other testing framework are accessible using the <code>special:</code> test descriptor. Currently, this includes <code>hotspot-internal</code>, <code>failure-handler</code> and <code>make</code>.</p>
|
||||
<p>A handful of odd tests that are not covered by any other testing framework are accessible using the <code>special:</code> test descriptor. Currently, this includes <code>failure-handler</code> and <code>make</code>.</p>
|
||||
<ul>
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||||
<li><p>Hotspot legacy internal testing (run using <code>-XX:+ExecuteInternalVMTests</code>) is run using <code>special:hotspot-internal</code> or just <code>hotspot-internal</code> as test descriptor, and will only work on a debug JVM.</p></li>
|
||||
<li><p>Failure handler testing is run using <code>special:failure-handler</code> or just <code>failure-handler</code> as test descriptor.</p></li>
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||||
<li><p>Tests for the build system, including both makefiles and related functionality, is run using <code>special:make</code> or just <code>make</code> as test descriptor. This is equivalent to <code>special:make:all</code>.</p>
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<p>A specific make test can be run by supplying it as argument, e.g. <code>special:make:idea</code>. As a special syntax, this can also be expressed as <code>make-idea</code>, which allows for command lines as <code>make test-make-idea</code>.</p></li>
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@ -108,11 +108,7 @@ present, then `gtest:all` will be equivalent to `gtest:all/server`.
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||||
|
||||
A handful of odd tests that are not covered by any other testing framework are
|
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accessible using the `special:` test descriptor. Currently, this includes
|
||||
`hotspot-internal`, `failure-handler` and `make`.
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||||
|
||||
* Hotspot legacy internal testing (run using `-XX:+ExecuteInternalVMTests`)
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||||
is run using `special:hotspot-internal` or just `hotspot-internal` as test
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descriptor, and will only work on a debug JVM.
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`failure-handler` and `make`.
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* Failure handler testing is run using `special:failure-handler` or just
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`failure-handler` as test descriptor.
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@ -485,7 +485,10 @@ endef
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||||
# ALL_NAMED_TESTS is defined in FindTests.gmk
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$(foreach t, $(ALL_NAMED_TESTS), $(eval $(call DeclareRunTestRecipe,$t)))
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ALL_TEST_TARGETS := $(addprefix test-, $(ALL_NAMED_TESTS))
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ALL_EXPLODED_TEST_TARGETS := $(addprefix exploded-test-, $(ALL_NAMED_TESTS))
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# We only support the "exploded-test-gtest" shortcut
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ALL_EXPLODED_TESTS := gtest
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ALL_EXPLODED_TEST_TARGETS := $(addprefix exploded-test-, $(ALL_EXPLODED_TESTS))
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ALL_TARGETS += $(ALL_TEST_TARGETS) $(ALL_EXPLODED_TEST_TARGETS)
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@ -687,16 +690,17 @@ else
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# copied and processed.
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java.desktop-gensrc-src: java.base-gensrc java.base-copy
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# The annotation processing for jdk.internal.vm.ci and jdk.internal.vm.compiler
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# needs classes from the current JDK.
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jdk.internal.vm.ci-gensrc-src: $(addsuffix -java, \
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$(call FindTransitiveDepsForModule, jdk.internal.vm.ci))
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# The annotation processing for jdk.internal.vm.compiler
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# and jdk.internal.vm.compiler.management needs classes from the current JDK.
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jdk.internal.vm.compiler-gensrc-src: $(addsuffix -java, \
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$(call FindTransitiveDepsForModule, jdk.internal.vm.compiler))
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jdk.internal.vm.compiler.management-gensrc-src: $(addsuffix -java, \
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$(call FindTransitiveDepsForModule, jdk.internal.vm.compiler.management))
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# For jdk.internal.vm.compiler, the gensrc step is generating a module-info.java.extra
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# For these modules, the gensrc step is generating a module-info.java.extra
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# file to be processed by the gensrc-moduleinfo target.
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jdk.internal.vm.compiler-gensrc-moduleinfo: jdk.internal.vm.compiler-gensrc-src
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jdk.internal.vm.compiler.management-gensrc-moduleinfo: jdk.internal.vm.compiler.management-gensrc-src
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jdk.jdeps-gendata: java rmic
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@ -852,7 +856,7 @@ else
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||||
# Declare dependency for all generated test targets
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$(foreach t, $(filter-out test-make%, $(ALL_TEST_TARGETS)), $(eval $t: jdk-image test-image))
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$(foreach t, $(filter-out exploded-test-make%, $(ALL_EXPLODED_TEST_TARGETS)), $(eval $t: exploded-image test-image))
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$(foreach t, $(ALL_EXPLODED_TEST_TARGETS), $(eval $t: exploded-image test-image))
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|
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create-buildjdk-copy: jdk.jlink-java java.base-gendata \
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$(addsuffix -java, $(INTERIM_IMAGE_MODULES))
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@ -1054,9 +1058,7 @@ ALL_TARGETS += default jdk images docs bundles all
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||||
|
||||
# Let "run-test" be an alias for "test"
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$(foreach t, $(ALL_NAMED_TESTS), $(eval run-test-$t: test-$t))
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$(foreach t, $(ALL_NAMED_TESTS), $(eval exploded-run-test-$t: exploded-test-$t))
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RUN_TEST_TARGETS := $(addprefix run-test-, $(ALL_NAMED_TESTS)) \
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$(addprefix exploded-run-test-, $(ALL_NAMED_TESTS))
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RUN_TEST_TARGETS := $(addprefix run-test-, $(ALL_NAMED_TESTS))
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run-test: test
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exploded-run-test: exploded-test
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@ -45,7 +45,7 @@ ifneq ($(TEST_VM_OPTS), )
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endif
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$(eval $(call ParseKeywordVariable, TEST_OPTS, \
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SINGLE_KEYWORDS := JOBS TIMEOUT_FACTOR, \
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SINGLE_KEYWORDS := JOBS TIMEOUT_FACTOR AOT_MODULES, \
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STRING_KEYWORDS := VM_OPTIONS JAVA_OPTIONS, \
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))
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@ -107,6 +107,90 @@ endif
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GTEST_LAUNCHER_DIRS := $(patsubst %/gtestLauncher, %, $(wildcard $(TEST_IMAGE_DIR)/hotspot/gtest/*/gtestLauncher))
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GTEST_VARIANTS := $(strip $(patsubst $(TEST_IMAGE_DIR)/hotspot/gtest/%, %, $(GTEST_LAUNCHER_DIRS)))
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||||
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||||
################################################################################
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||||
# Optionally create AOT libraries for specified modules before running tests.
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||||
# Note, this could not be done during JDK build time.
|
||||
################################################################################
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||||
|
||||
# Note, this could not be done during JDK build time.
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||||
|
||||
# Parameter 1 is the name of the rule.
|
||||
#
|
||||
# Remaining parameters are named arguments.
|
||||
# MODULE The module to generate a library for
|
||||
# BIN Output directory in which to put the library
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# VM_OPTIONS List of JVM arguments to use when creating library
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# OPTIONS_VAR Name of variable to put AOT java options in
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# PREREQS_VAR Name of variable to put all AOT prerequisite rule targets in
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# for test rules to depend on
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#
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SetupAotModule = $(NamedParamsMacroTemplate)
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define SetupAotModuleBody
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$1_AOT_LIB := $$($1_BIN)/$$(call SHARED_LIBRARY,$$($1_MODULE))
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$1_AOT_CCLIST := $$(wildcard $$(TOPDIR)/test/hotspot/jtreg/compiler/aot/scripts/$$($1_MODULE)-list.txt)
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||||
ifeq ($(OPENJDK_TARGET_OS), windows)
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||||
$1_LD := $$(addsuffix $$(EXE_SUFFIX), $$(filter-out $$(FIXPATH), $$(LD)))
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||||
else
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||||
$1_LD := $$(LD)
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||||
endif
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||||
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||||
$1_JAOTC_OPTS := \
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-J-Xmx4g --info \
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$$(addprefix -J, $$($1_VM_OPTIONS)) \
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$$(addprefix --compile-commands$(SPACE), $$($1_AOT_CCLIST)) \
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--linker-path $$($1_LD) \
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#
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ifneq ($$(filter -ea, $$($1_VM_OPTIONS)), )
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$1_JAOTC_OPTS += --compile-with-assertions
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endif
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||||
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||||
$$($1_AOT_LIB): $$(JDK_IMAGE_DIR)/release \
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$$(call DependOnVariable, $1_JAOTC_OPTS) \
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$$(call DependOnVariable, JDK_IMAGE_DIR)
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$$(call LogWarn, Generating $$(patsubst $$(OUTPUTDIR)/%, %, $$@))
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||||
$$(call MakeTargetDir)
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||||
$$(call ExecuteWithLog, $$@, \
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$$(FIXPATH) $$(JDK_IMAGE_DIR)/bin/jaotc \
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$$($1_JAOTC_OPTS) --output $$@ --module $$($1_MODULE) \
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)
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||||
$$(call ExecuteWithLog, $$@.check, \
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$$(FIXPATH) $$(JDK_IMAGE_DIR)/bin/java \
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$$($1_VM_OPTIONS) -XX:+PrintAOT -XX:+UseAOTStrictLoading -XX:AOTLibrary=$$@ -version \
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> $$@.verify-aot \
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)
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$1_AOT_OPTIONS += -XX:AOTLibrary=$$($1_AOT_LIB)
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$1_AOT_TARGETS += $$($1_AOT_LIB)
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endef
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# Parameter 1 is the name of the rule.
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||||
#
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||||
# Remaining parameters are named arguments.
|
||||
# MODULES The modules to generate a library for
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||||
# VM_OPTIONS List of JVM arguments to use when creating libraries
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||||
#
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||||
# After calling this, the following variables are defined
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# $1_AOT_OPTIONS List of all java options needed to use the AOT libraries
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# $1_AOT_TARGETS List of all targets that the test rule will need to depend on
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#
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SetupAot = $(NamedParamsMacroTemplate)
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define SetupAotBody
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$$(info Running with AOTd libraries for $$($1_MODULES))
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# Put aot libraries in a separate directory so they are not deleted between
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||||
# test runs and may be reused between make invocations.
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||||
$$(foreach m, $$($1_MODULES), \
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$$(eval $$(call SetupAotModule, $1_$$m, \
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MODULE := $$m, \
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BIN := $$(TEST_SUPPORT_DIR)/aot/$1, \
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VM_OPTIONS := $$($1_VM_OPTIONS), \
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)) \
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||||
$$(eval $1_AOT_OPTIONS += $$($1_$$m_AOT_OPTIONS)) \
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$$(eval $1_AOT_TARGETS += $$($1_$$m_AOT_TARGETS)) \
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)
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||||
endef
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||||
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||||
################################################################################
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||||
# Setup global test running parameters
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||||
################################################################################
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@ -146,12 +230,15 @@ $(eval $(call SetTestOpt,JAVA_OPTIONS,JTREG))
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$(eval $(call SetTestOpt,VM_OPTIONS,GTEST))
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$(eval $(call SetTestOpt,JAVA_OPTIONS,GTEST))
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$(eval $(call SetTestOpt,AOT_MODULES,JTREG))
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$(eval $(call SetTestOpt,AOT_MODULES,GTEST))
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$(eval $(call SetTestOpt,JOBS,JTREG))
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$(eval $(call SetTestOpt,TIMEOUT_FACTOR,JTREG))
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||||
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$(eval $(call ParseKeywordVariable, JTREG, \
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||||
SINGLE_KEYWORDS := JOBS TIMEOUT_FACTOR TEST_MODE ASSERT VERBOSE RETAIN MAX_MEM \
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||||
EXTRA_PROBLEM_LISTS KEYWORDS, \
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||||
EXTRA_PROBLEM_LISTS KEYWORDS AOT_MODULES, \
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||||
STRING_KEYWORDS := OPTIONS JAVA_OPTIONS VM_OPTIONS, \
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||||
))
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||||
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||||
@ -161,7 +248,7 @@ ifneq ($(JTREG), )
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||||
endif
|
||||
|
||||
$(eval $(call ParseKeywordVariable, GTEST, \
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||||
SINGLE_KEYWORDS := REPEAT, \
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||||
SINGLE_KEYWORDS := REPEAT AOT_MODULES, \
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||||
STRING_KEYWORDS := OPTIONS VM_OPTIONS JAVA_OPTIONS, \
|
||||
))
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||||
|
||||
@ -318,7 +405,7 @@ define ParseSpecialTestSelection
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||||
special:make:all \
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)
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||||
) \
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||||
$(if $(filter hotspot-internal failure-handler, $1), \
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||||
$(if $(filter failure-handler, $1), \
|
||||
special:$(strip $1) \
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||||
)
|
||||
endef
|
||||
@ -407,7 +494,14 @@ define SetupRunGtestTestBody
|
||||
$1_GTEST_REPEAT :=--gtest_repeat=$$(GTEST_REPEAT)
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||||
endif
|
||||
|
||||
run-test-$1: $(TEST_PREREQS)
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||||
ifneq ($$(GTEST_AOT_MODULES), )
|
||||
$$(eval $$(call SetupAot, $1, \
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MODULES := $$(GTEST_AOT_MODULES), \
|
||||
VM_OPTIONS := $$(GTEST_VM_OPTIONS) $$(GTEST_JAVA_OPTIONS), \
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||||
))
|
||||
endif
|
||||
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run-test-$1: $$($1_AOT_TARGETS)
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$$(call LogWarn)
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||||
$$(call LogWarn, Running test '$$($1_TEST)')
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||||
$$(call MakeDir, $$($1_TEST_RESULTS_DIR) $$($1_TEST_SUPPORT_DIR))
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||||
@ -416,7 +510,7 @@ define SetupRunGtestTestBody
|
||||
-jdk $(JDK_IMAGE_DIR) $$($1_GTEST_FILTER) \
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||||
--gtest_output=xml:$$($1_TEST_RESULTS_DIR)/gtest.xml \
|
||||
$$($1_GTEST_REPEAT) $$(GTEST_OPTIONS) $$(GTEST_VM_OPTIONS) \
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||||
$$($1_GTEST_JAVA_OPTIONS) \
|
||||
$$(GTEST_JAVA_OPTIONS) $$($1_AOT_OPTIONS) \
|
||||
> >($(TEE) $$($1_TEST_RESULTS_DIR)/gtest.txt) \
|
||||
&& $$(ECHO) $$$$? > $$($1_EXITCODE) \
|
||||
|| $$(ECHO) $$$$? > $$($1_EXITCODE) \
|
||||
@ -600,10 +694,21 @@ define SetupRunJtregTestBody
|
||||
endif
|
||||
endif
|
||||
|
||||
ifneq ($$(JTREG_AOT_MODULES), )
|
||||
$$(eval $$(call SetupAot, $1, \
|
||||
MODULES := $$(JTREG_AOT_MODULES), \
|
||||
VM_OPTIONS := $$(JTREG_VM_OPTIONS) $$(JTREG_JAVA_OPTIONS), \
|
||||
))
|
||||
endif
|
||||
|
||||
ifneq ($$($1_AOT_OPTIONS), )
|
||||
$1_JTREG_BASIC_OPTIONS += -vmoptions:"$$($1_AOT_OPTIONS)"
|
||||
endif
|
||||
|
||||
clean-workdir-$1:
|
||||
$$(RM) -r $$($1_TEST_SUPPORT_DIR)
|
||||
|
||||
run-test-$1: clean-workdir-$1 $(TEST_PREREQS)
|
||||
run-test-$1: clean-workdir-$1 $$($1_AOT_TARGETS)
|
||||
$$(call LogWarn)
|
||||
$$(call LogWarn, Running test '$$($1_TEST)')
|
||||
$$(call MakeDir, $$($1_TEST_RESULTS_DIR) $$($1_TEST_SUPPORT_DIR))
|
||||
@ -674,11 +779,7 @@ define SetupRunSpecialTestBody
|
||||
$1_TEST_ARGS :=
|
||||
endif
|
||||
|
||||
ifeq ($$($1_TEST_NAME), hotspot-internal)
|
||||
$1_TEST_COMMAND_LINE := \
|
||||
$$(JDK_IMAGE_DIR)/bin/java -XX:+ExecuteInternalVMTests \
|
||||
-XX:+ShowMessageBoxOnError -version
|
||||
else ifeq ($$($1_TEST_NAME), failure-handler)
|
||||
ifeq ($$($1_TEST_NAME), failure-handler)
|
||||
ifeq ($(BUILD_FAILURE_HANDLER), true)
|
||||
$1_TEST_COMMAND_LINE := \
|
||||
($(CD) $(TOPDIR)/make/test && $(MAKE) $(MAKE_ARGS) -f \
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
#
|
||||
# Copyright (c) 2017, Oracle and/or its affiliates. All rights reserved.
|
||||
# Copyright (c) 2017, 2018, Oracle and/or its affiliates. All rights reserved.
|
||||
# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
|
||||
#
|
||||
# This code is free software; you can redistribute it and/or modify it
|
||||
@ -95,12 +95,12 @@ endef
|
||||
# $1: The output file name
|
||||
# $2..$N: The lines to output to the file
|
||||
define CreateNewSpec
|
||||
$(if $(strip $(26)), \
|
||||
$(if $(strip $(30)), \
|
||||
$(error Internal makefile error: \
|
||||
Too many arguments to macro, please update CreateNewSpec in RunTestsPrebuilt.gmk) \
|
||||
) \
|
||||
$(shell $(RM) $1) \
|
||||
$(foreach i, $(call sequence, 2, 25), \
|
||||
$(foreach i, $(call sequence, 2, 29), \
|
||||
$(if $(strip $($i)), \
|
||||
$(call AppendFile, $(strip $($i)), $1) \
|
||||
) \
|
||||
@ -235,6 +235,34 @@ ifeq ($(NUM_CORES), )
|
||||
NUM_CORES := 1
|
||||
endif
|
||||
|
||||
# Setup LD for AOT support
|
||||
ifneq ($(DEVKIT_HOME), )
|
||||
ifeq ($(OPENJDK_TARGET_OS), windows)
|
||||
LD := $(DEVKIT_HOME)/VC/bin/x64/link
|
||||
LIBRARY_PREFIX :=
|
||||
SHARED_LIBRARY_SUFFIX := .dll
|
||||
EXE_SUFFIX := .exe
|
||||
else ifeq ($(OPENJDK_TARGET_OS), linux)
|
||||
LD := $(DEVKIT_HOME)/bin/ld
|
||||
LIBRARY_PREFIX := lib
|
||||
SHARED_LIBRARY_SUFFIX := .so
|
||||
EXE_SUFFIX :=
|
||||
else ifeq ($(OPENJDK_TARGET_OS), macosx)
|
||||
LD := $(DEVKIT_HOME)/Xcode.app/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/bin/ld
|
||||
LIBRARY_PREFIX := lib
|
||||
SHARED_LIBRARY_SUFFIX := .dylib
|
||||
EXE_SUFFIX :=
|
||||
else ifeq ($(OPENJDK_TARGET_OS), solaris)
|
||||
# Prefer system linker for AOT on Solaris.
|
||||
LD := ld
|
||||
LIBRARY_PREFIX := lib
|
||||
SHARED_LIBRARY_SUFFIX := .so
|
||||
EXE_SUFFIX :=
|
||||
endif
|
||||
else
|
||||
LD := ld
|
||||
endif
|
||||
|
||||
################################################################################
|
||||
# Generate the ephemeral spec file
|
||||
################################################################################
|
||||
@ -270,6 +298,10 @@ $(call CreateNewSpec, $(NEW_SPEC), \
|
||||
OPENJDK_TARGET_CPU_BITS := $(OPENJDK_TARGET_CPU_BITS), \
|
||||
OPENJDK_TARGET_CPU_ENDIAN := $(OPENJDK_TARGET_CPU_ENDIAN), \
|
||||
NUM_CORES := $(NUM_CORES), \
|
||||
LD := $(LD), \
|
||||
LIBRARY_PREFIX := $(LIBRARY_PREFIX), \
|
||||
SHARED_LIBRARY_SUFFIX := $(SHARED_LIBRARY_SUFFIX), \
|
||||
EXE_SUFFIX := $(EXE_SUFFIX), \
|
||||
include $(TOPDIR)/make/RunTestsPrebuiltSpec.gmk, \
|
||||
$(CUSTOM_NEW_SPEC_LINE), \
|
||||
)
|
||||
|
||||
@ -186,3 +186,7 @@ endif
|
||||
ifeq ($(OPENJDK_BUILD_OS), windows)
|
||||
CYGPATH := cygpath
|
||||
endif
|
||||
|
||||
################################################################################
|
||||
# Simple macros from spec.gmk.in
|
||||
SHARED_LIBRARY=$(LIBRARY_PREFIX)$1$(SHARED_LIBRARY_SUFFIX)
|
||||
|
||||
@ -186,6 +186,9 @@ AC_DEFUN_ONCE([LIB_SETUP_FREETYPE],
|
||||
FREETYPE_BASE_DIR="$SYSROOT/usr"
|
||||
if (test "x$OPENJDK_TARGET_CPU_BITS" = "x64"); then
|
||||
LIB_CHECK_POTENTIAL_FREETYPE([$FREETYPE_BASE_DIR/include], [$FREETYPE_BASE_DIR/lib/$OPENJDK_TARGET_CPU-linux-gnu], [well-known location])
|
||||
if (test "x$FOUND_FREETYPE" != "xyes"); then
|
||||
LIB_CHECK_POTENTIAL_FREETYPE([$FREETYPE_BASE_DIR/include], [$FREETYPE_BASE_DIR/lib64], [well-known location])
|
||||
fi
|
||||
else
|
||||
LIB_CHECK_POTENTIAL_FREETYPE([$FREETYPE_BASE_DIR/include], [$FREETYPE_BASE_DIR/lib/i386-linux-gnu], [well-known location])
|
||||
if (test "x$FOUND_FREETYPE" != "xyes"); then
|
||||
|
||||
@ -79,7 +79,7 @@ MAKE_TEST_TARGETS := $(shell $(MAKE) -s --no-print-directory $(MAKE_ARGS) \
|
||||
ALL_NAMED_TESTS += $(addprefix make-, $(MAKE_TEST_TARGETS))
|
||||
|
||||
# Add special tests
|
||||
ALL_NAMED_TESTS += hotspot-internal failure-handler make
|
||||
ALL_NAMED_TESTS += failure-handler make
|
||||
|
||||
################################################################################
|
||||
|
||||
|
||||
@ -201,10 +201,15 @@ var getJibProfiles = function (input) {
|
||||
data.configuration_make_arg = "CONF_NAME=";
|
||||
|
||||
// Exclude list to use when Jib creates a source bundle
|
||||
data.src_bundle_excludes = "./build .build webrev* */webrev* */*/webrev* */*/*/webrev* .hg */.hg */*/.hg */*/*/.hg";
|
||||
data.src_bundle_excludes = [
|
||||
"build", "{,**/}webrev*", "{,**/}.hg", "{,**/}JTwork", "{,**/}JTreport",
|
||||
"{,**/}.git"
|
||||
];
|
||||
// Include list to use when creating a minimal jib source bundle which
|
||||
// contains just the jib configuration files.
|
||||
data.conf_bundle_includes = "*/conf/jib-profiles.* make/autoconf/version-numbers"
|
||||
data.conf_bundle_includes = [
|
||||
"make/autoconf/version-numbers",
|
||||
];
|
||||
|
||||
// Define some common values
|
||||
var common = getJibProfilesCommon(input, data);
|
||||
@ -485,7 +490,7 @@ var getJibProfilesProfiles = function (input, common, data) {
|
||||
.forEach(function (name) {
|
||||
var maketestName = name + "-testmake";
|
||||
profiles[maketestName] = concatObjects(profiles[name], testmakeBase);
|
||||
profiles[maketestName].default_make_targets = [ "test-make", "test-compile-commands" ];
|
||||
profiles[maketestName].default_make_targets = [ "test-make" ];
|
||||
});
|
||||
|
||||
// Profiles for building the zero jvm variant. These are used for verification.
|
||||
@ -522,6 +527,27 @@ var getJibProfilesProfiles = function (input, common, data) {
|
||||
profiles[debugName] = concatObjects(profiles[name], common.debug_profile_base);
|
||||
});
|
||||
|
||||
// Define a profile with precompiled headers disabled. This is just used for
|
||||
// verfication of this build configuration.
|
||||
var noPchProfiles = {
|
||||
"linux-x64-debug-nopch": {
|
||||
target_os: "linux",
|
||||
target_cpu: "x64",
|
||||
dependencies: ["devkit"],
|
||||
configure_args: concat(common.configure_args_64bit,
|
||||
"--with-zlib=system", "--disable-precompiled-headers"),
|
||||
},
|
||||
};
|
||||
profiles = concatObjects(profiles, noPchProfiles);
|
||||
// Add base settings to noPch profiles
|
||||
Object.keys(noPchProfiles).forEach(function (name) {
|
||||
profiles[name] = concatObjects(common.main_profile_base, profiles[name]);
|
||||
profiles[name] = concatObjects(common.debug_profile_base, profiles[name]);
|
||||
// Override default make target with hotspot as that's the only part of
|
||||
// the build using precompiled headers.
|
||||
profiles[name].default_make_targets = ["hotspot"];
|
||||
});
|
||||
|
||||
// Bootcycle profiles runs the build with itself as the boot jdk. This can
|
||||
// be done in two ways. Either using the builtin bootcycle target in the
|
||||
// build system. Or by supplying the main jdk build as bootjdk to configure.
|
||||
@ -709,7 +735,8 @@ var getJibProfilesProfiles = function (input, common, data) {
|
||||
"run-test-prebuilt": {
|
||||
target_os: input.build_os,
|
||||
target_cpu: input.build_cpu,
|
||||
dependencies: [ "jtreg", "gnumake", "boot_jdk", "jib", testedProfile + ".jdk",
|
||||
dependencies: [
|
||||
"jtreg", "gnumake", "boot_jdk", "devkit", "jib", testedProfile + ".jdk",
|
||||
testedProfile + ".test"
|
||||
],
|
||||
src: "src.conf",
|
||||
@ -743,7 +770,6 @@ var getJibProfilesProfiles = function (input, common, data) {
|
||||
// This gives us a guaranteed working version of lldb for the jtreg failure handler.
|
||||
if (input.build_os == "macosx") {
|
||||
macosxRunTestExtra = {
|
||||
dependencies: [ "devkit" ],
|
||||
environment_path: input.get("devkit", "install_path")
|
||||
+ "/Xcode.app/Contents/Developer/usr/bin"
|
||||
};
|
||||
@ -836,7 +862,10 @@ var getJibProfilesDependencies = function (input, common) {
|
||||
organization: common.organization,
|
||||
ext: "tar.gz",
|
||||
module: "devkit-" + devkit_platform,
|
||||
revision: devkit_platform_revisions[devkit_platform]
|
||||
revision: devkit_platform_revisions[devkit_platform],
|
||||
environment: {
|
||||
"DEVKIT_HOME": input.get("devkit", "home_path"),
|
||||
}
|
||||
},
|
||||
|
||||
build_devkit: {
|
||||
@ -937,14 +966,6 @@ var getJibProfilesDependencies = function (input, common) {
|
||||
},
|
||||
};
|
||||
|
||||
// Need to add a value for the Visual Studio tools variable to make
|
||||
// jaot be able to pick up the Visual Studio linker in testing.
|
||||
if (input.target_os == "windows") {
|
||||
dependencies.devkit.environment = {
|
||||
VS120COMNTOOLS: input.get("devkit", "install_path") + "/Common7/Tools"
|
||||
};
|
||||
}
|
||||
|
||||
return dependencies;
|
||||
};
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2017, Oracle and/or its affiliates. All rights reserved.
|
||||
* Copyright (c) 2017, 2018, Oracle and/or its affiliates. All rights reserved.
|
||||
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
|
||||
*
|
||||
* This code is free software; you can redistribute it and/or modify it
|
||||
@ -127,3 +127,14 @@ tr:nth-child(odd), tr:nth-child(odd) th[scope=row] {
|
||||
th {
|
||||
background: #DDF;
|
||||
}
|
||||
|
||||
table.centered {
|
||||
margin-left: auto;
|
||||
margin-right: auto;
|
||||
}
|
||||
table.centered td {
|
||||
text-align: left;
|
||||
}
|
||||
.centered {
|
||||
text-align: center;
|
||||
}
|
||||
|
||||
@ -21,4 +21,4 @@
|
||||
# or visit www.oracle.com if you need additional information or have any
|
||||
# questions.
|
||||
#
|
||||
tzdata2018e
|
||||
tzdata2018g
|
||||
|
||||
@ -21,6 +21,8 @@
|
||||
# or visit www.oracle.com if you need additional information or have any
|
||||
# questions.
|
||||
#
|
||||
# tzdb data for Africa and environs
|
||||
|
||||
# This file is in the public domain, so clarified as of
|
||||
# 2009-05-17 by Arthur David Olson.
|
||||
|
||||
@ -29,7 +31,7 @@
|
||||
# tz@iana.org for general use in the future). For more, please see
|
||||
# the file CONTRIBUTING in the tz distribution.
|
||||
|
||||
# From Paul Eggert (2017-04-09):
|
||||
# From Paul Eggert (2018-05-27):
|
||||
#
|
||||
# Unless otherwise specified, the source for data through 1990 is:
|
||||
# Thomas G. Shanks and Rique Pottenger, The International Atlas (6th edition),
|
||||
@ -74,13 +76,15 @@
|
||||
# I vaguely recall 'WAT' also being used for -01 in the past but
|
||||
# cannot now come up with solid citations.
|
||||
#
|
||||
# I invented the following abbreviations; corrections are welcome!
|
||||
# +02 WAST West Africa Summer Time (no longer used)
|
||||
# +03 CAST Central Africa Summer Time (no longer used)
|
||||
# +03 SAST South Africa Summer Time (no longer used)
|
||||
# I invented the following abbreviations in the 1990s:
|
||||
# +02 WAST West Africa Summer Time
|
||||
# +03 CAST Central Africa Summer Time
|
||||
# +03 SAST South Africa Summer Time
|
||||
# +03 EAT East Africa Time
|
||||
# 'EAT' also seems to have caught on; the others are rare but are paired
|
||||
# with better-attested non-DST abbreviations.
|
||||
# 'EAT' seems to have caught on and is in current timestamps, and though
|
||||
# the other abbreviations are rarer and are only in past timestamps,
|
||||
# they are paired with better-attested non-DST abbreviations.
|
||||
# Corrections are welcome.
|
||||
|
||||
# Algeria
|
||||
# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S
|
||||
@ -385,6 +389,13 @@ Zone Africa/Cairo 2:05:09 - LMT 1900 Oct
|
||||
# Eritrea
|
||||
# Ethiopia
|
||||
# See Africa/Nairobi.
|
||||
#
|
||||
# Unfortunately tzdb records only Western clock time in use in Ethiopia,
|
||||
# as the tzdb format is not up to properly recording a common Ethiopian
|
||||
# timekeeping practice that is based on solar time. See:
|
||||
# Mortada D. If you have a meeting in Ethiopia, you'd better double
|
||||
# check the time. PRI's The World. 2015-01-30 15:15 -05.
|
||||
# https://www.pri.org/stories/2015-01-30/if-you-have-meeting-ethiopia-you-better-double-check-time
|
||||
|
||||
# Gabon
|
||||
# See Africa/Lagos.
|
||||
@ -856,94 +867,61 @@ Zone Indian/Mauritius 3:50:00 - LMT 1907 # Port Louis
|
||||
# <https://lnt.ma/le-maroc-reculera-dune-heure-le-dimanche-14-juin/> agrees
|
||||
# with the patch.
|
||||
|
||||
# From Paul Eggert (2015-06-08):
|
||||
# For now, guess that later spring and fall transitions will use 2015's rules,
|
||||
# and guess that Morocco will switch to standard time at 03:00 the last
|
||||
# Sunday before Ramadan, and back to DST at 02:00 the first Sunday after
|
||||
# Ramadan. To implement this, transition dates for 2016 through 2037 were
|
||||
# determined by running the following program under GNU Emacs 24.3, with the
|
||||
# results integrated by hand into the table below.
|
||||
# (let ((islamic-year 1437))
|
||||
# (require 'cal-islam)
|
||||
# (while (< islamic-year 1460)
|
||||
# (let ((a (calendar-islamic-to-absolute (list 9 1 islamic-year)))
|
||||
# (b (calendar-islamic-to-absolute (list 10 1 islamic-year)))
|
||||
# (sunday 0))
|
||||
# (while (/= sunday (mod (setq a (1- a)) 7)))
|
||||
# (while (/= sunday (mod b 7))
|
||||
# (setq b (1+ b)))
|
||||
# (setq a (calendar-gregorian-from-absolute a))
|
||||
# (setq b (calendar-gregorian-from-absolute b))
|
||||
# (insert
|
||||
# (format
|
||||
# (concat "Rule\tMorocco\t%d\tonly\t-\t%s\t%2d\t 3:00\t0\t-\n"
|
||||
# "Rule\tMorocco\t%d\tonly\t-\t%s\t%2d\t 2:00\t1:00\tS\n")
|
||||
# (car (cdr (cdr a))) (calendar-month-name (car a) t) (car (cdr a))
|
||||
# (car (cdr (cdr b))) (calendar-month-name (car b) t) (car (cdr b)))))
|
||||
# (setq islamic-year (+ 1 islamic-year))))
|
||||
# From Mohamed Essedik Najd (2018-10-26):
|
||||
# Today, a Moroccan government council approved the perpetual addition
|
||||
# of 60 minutes to the regular Moroccan timezone.
|
||||
# From Brian Inglis (2018-10-26):
|
||||
# http://www.maroc.ma/fr/actualites/le-conseil-de-gouvernement-adopte-un-projet-de-decret-relatif-lheure-legale-stipulant-le
|
||||
|
||||
# RULE NAME FROM TO TYPE IN ON AT SAVE LETTER/S
|
||||
|
||||
Rule Morocco 1939 only - Sep 12 0:00 1:00 S
|
||||
Rule Morocco 1939 only - Sep 12 0:00 1:00 -
|
||||
Rule Morocco 1939 only - Nov 19 0:00 0 -
|
||||
Rule Morocco 1940 only - Feb 25 0:00 1:00 S
|
||||
Rule Morocco 1940 only - Feb 25 0:00 1:00 -
|
||||
Rule Morocco 1945 only - Nov 18 0:00 0 -
|
||||
Rule Morocco 1950 only - Jun 11 0:00 1:00 S
|
||||
Rule Morocco 1950 only - Jun 11 0:00 1:00 -
|
||||
Rule Morocco 1950 only - Oct 29 0:00 0 -
|
||||
Rule Morocco 1967 only - Jun 3 12:00 1:00 S
|
||||
Rule Morocco 1967 only - Jun 3 12:00 1:00 -
|
||||
Rule Morocco 1967 only - Oct 1 0:00 0 -
|
||||
Rule Morocco 1974 only - Jun 24 0:00 1:00 S
|
||||
Rule Morocco 1974 only - Jun 24 0:00 1:00 -
|
||||
Rule Morocco 1974 only - Sep 1 0:00 0 -
|
||||
Rule Morocco 1976 1977 - May 1 0:00 1:00 S
|
||||
Rule Morocco 1976 1977 - May 1 0:00 1:00 -
|
||||
Rule Morocco 1976 only - Aug 1 0:00 0 -
|
||||
Rule Morocco 1977 only - Sep 28 0:00 0 -
|
||||
Rule Morocco 1978 only - Jun 1 0:00 1:00 S
|
||||
Rule Morocco 1978 only - Jun 1 0:00 1:00 -
|
||||
Rule Morocco 1978 only - Aug 4 0:00 0 -
|
||||
Rule Morocco 2008 only - Jun 1 0:00 1:00 S
|
||||
Rule Morocco 2008 only - Jun 1 0:00 1:00 -
|
||||
Rule Morocco 2008 only - Sep 1 0:00 0 -
|
||||
Rule Morocco 2009 only - Jun 1 0:00 1:00 S
|
||||
Rule Morocco 2009 only - Jun 1 0:00 1:00 -
|
||||
Rule Morocco 2009 only - Aug 21 0:00 0 -
|
||||
Rule Morocco 2010 only - May 2 0:00 1:00 S
|
||||
Rule Morocco 2010 only - May 2 0:00 1:00 -
|
||||
Rule Morocco 2010 only - Aug 8 0:00 0 -
|
||||
Rule Morocco 2011 only - Apr 3 0:00 1:00 S
|
||||
Rule Morocco 2011 only - Apr 3 0:00 1:00 -
|
||||
Rule Morocco 2011 only - Jul 31 0:00 0 -
|
||||
Rule Morocco 2012 2013 - Apr lastSun 2:00 1:00 S
|
||||
Rule Morocco 2012 2013 - Apr lastSun 2:00 1:00 -
|
||||
Rule Morocco 2012 only - Jul 20 3:00 0 -
|
||||
Rule Morocco 2012 only - Aug 20 2:00 1:00 S
|
||||
Rule Morocco 2012 only - Aug 20 2:00 1:00 -
|
||||
Rule Morocco 2012 only - Sep 30 3:00 0 -
|
||||
Rule Morocco 2013 only - Jul 7 3:00 0 -
|
||||
Rule Morocco 2013 only - Aug 10 2:00 1:00 S
|
||||
Rule Morocco 2013 max - Oct lastSun 3:00 0 -
|
||||
Rule Morocco 2014 2021 - Mar lastSun 2:00 1:00 S
|
||||
Rule Morocco 2013 only - Aug 10 2:00 1:00 -
|
||||
Rule Morocco 2013 2018 - Oct lastSun 3:00 0 -
|
||||
Rule Morocco 2014 2018 - Mar lastSun 2:00 1:00 -
|
||||
Rule Morocco 2014 only - Jun 28 3:00 0 -
|
||||
Rule Morocco 2014 only - Aug 2 2:00 1:00 S
|
||||
Rule Morocco 2014 only - Aug 2 2:00 1:00 -
|
||||
Rule Morocco 2015 only - Jun 14 3:00 0 -
|
||||
Rule Morocco 2015 only - Jul 19 2:00 1:00 S
|
||||
Rule Morocco 2015 only - Jul 19 2:00 1:00 -
|
||||
Rule Morocco 2016 only - Jun 5 3:00 0 -
|
||||
Rule Morocco 2016 only - Jul 10 2:00 1:00 S
|
||||
Rule Morocco 2016 only - Jul 10 2:00 1:00 -
|
||||
Rule Morocco 2017 only - May 21 3:00 0 -
|
||||
Rule Morocco 2017 only - Jul 2 2:00 1:00 S
|
||||
Rule Morocco 2017 only - Jul 2 2:00 1:00 -
|
||||
Rule Morocco 2018 only - May 13 3:00 0 -
|
||||
Rule Morocco 2018 only - Jun 17 2:00 1:00 S
|
||||
Rule Morocco 2019 only - May 5 3:00 0 -
|
||||
Rule Morocco 2019 only - Jun 9 2:00 1:00 S
|
||||
Rule Morocco 2020 only - Apr 19 3:00 0 -
|
||||
Rule Morocco 2020 only - May 24 2:00 1:00 S
|
||||
Rule Morocco 2021 only - Apr 11 3:00 0 -
|
||||
Rule Morocco 2021 only - May 16 2:00 1:00 S
|
||||
Rule Morocco 2022 only - May 8 2:00 1:00 S
|
||||
Rule Morocco 2023 only - Apr 23 2:00 1:00 S
|
||||
Rule Morocco 2024 only - Apr 14 2:00 1:00 S
|
||||
Rule Morocco 2025 only - Apr 6 2:00 1:00 S
|
||||
Rule Morocco 2026 max - Mar lastSun 2:00 1:00 S
|
||||
Rule Morocco 2036 only - Oct 19 3:00 0 -
|
||||
Rule Morocco 2037 only - Oct 4 3:00 0 -
|
||||
Rule Morocco 2018 only - Jun 17 2:00 1:00 -
|
||||
|
||||
# Zone NAME GMTOFF RULES FORMAT [UNTIL]
|
||||
Zone Africa/Casablanca -0:30:20 - LMT 1913 Oct 26
|
||||
0:00 Morocco WE%sT 1984 Mar 16
|
||||
1:00 - CET 1986
|
||||
0:00 Morocco WE%sT
|
||||
0:00 Morocco +00/+01 1984 Mar 16
|
||||
1:00 - +01 1986
|
||||
0:00 Morocco +00/+01 2018 Oct 27
|
||||
1:00 - +01
|
||||
|
||||
# Western Sahara
|
||||
#
|
||||
@ -958,7 +936,8 @@ Zone Africa/Casablanca -0:30:20 - LMT 1913 Oct 26
|
||||
|
||||
Zone Africa/El_Aaiun -0:52:48 - LMT 1934 Jan # El Aaiún
|
||||
-1:00 - -01 1976 Apr 14
|
||||
0:00 Morocco WE%sT
|
||||
0:00 Morocco +00/+01 2018 Oct 27
|
||||
1:00 - +01
|
||||
|
||||
# Mozambique
|
||||
#
|
||||
|
||||
@ -21,6 +21,8 @@
|
||||
# or visit www.oracle.com if you need additional information or have any
|
||||
# questions.
|
||||
#
|
||||
# tzdb data for Antarctica and environs
|
||||
|
||||
# This file is in the public domain, so clarified as of
|
||||
# 2009-05-17 by Arthur David Olson.
|
||||
|
||||
|
||||
@ -21,6 +21,8 @@
|
||||
# or visit www.oracle.com if you need additional information or have any
|
||||
# questions.
|
||||
#
|
||||
# tzdb data for Asia and environs
|
||||
|
||||
# This file is in the public domain, so clarified as of
|
||||
# 2009-05-17 by Arthur David Olson.
|
||||
|
||||
@ -29,7 +31,7 @@
|
||||
# tz@iana.org for general use in the future). For more, please see
|
||||
# the file CONTRIBUTING in the tz distribution.
|
||||
|
||||
# From Paul Eggert (2017-01-13):
|
||||
# From Paul Eggert (2018-06-19):
|
||||
#
|
||||
# Unless otherwise specified, the source for data through 1990 is:
|
||||
# Thomas G. Shanks and Rique Pottenger, The International Atlas (6th edition),
|
||||
@ -58,7 +60,8 @@
|
||||
# A reliable and entertaining source about time zones is
|
||||
# Derek Howse, Greenwich time and longitude, Philip Wilson Publishers (1997).
|
||||
#
|
||||
# The following alphabetic abbreviations appear in these tables:
|
||||
# The following alphabetic abbreviations appear in these tables
|
||||
# (corrections are welcome):
|
||||
# std dst
|
||||
# LMT Local Mean Time
|
||||
# 2:00 EET EEST Eastern European Time
|
||||
@ -67,11 +70,13 @@
|
||||
# 7:00 WIB west Indonesia (Waktu Indonesia Barat)
|
||||
# 8:00 WITA central Indonesia (Waktu Indonesia Tengah)
|
||||
# 8:00 CST China
|
||||
# 8:00 PST PDT* Philippine Standard Time
|
||||
# 8:30 KST KDT Korea when at +0830
|
||||
# 9:00 WIT east Indonesia (Waktu Indonesia Timur)
|
||||
# 9:00 JST JDT Japan
|
||||
# 9:00 KST KDT Korea when at +09
|
||||
# 9:30 ACST Australian Central Standard Time
|
||||
# *I invented the abbreviation PDT; see "Philippines" below.
|
||||
# Otherwise, these tables typically use numeric abbreviations like +03
|
||||
# and +0330 for integer hour and minute UT offsets. Although earlier
|
||||
# editions invented alphabetic time zone abbreviations for every
|
||||
@ -304,6 +309,29 @@ Zone Asia/Yangon 6:24:47 - LMT 1880 # or Rangoon
|
||||
|
||||
# China
|
||||
|
||||
# From Paul Eggert (2018-10-02):
|
||||
# The following comes from Table 1 of:
|
||||
# Li Yu. Research on the daylight saving movement in 1940s Shanghai.
|
||||
# Nanjing Journal of Social Sciences. 2014;(2):144-50.
|
||||
# http://oversea.cnki.net/kns55/detail.aspx?dbname=CJFD2014&filename=NJSH201402020
|
||||
# The table lists dates only; I am guessing 00:00 and 24:00 transition times.
|
||||
# Also, the table lists the planned end of DST in 1949, but the corresponding
|
||||
# zone line cuts this off on May 28, when the Communists took power.
|
||||
#
|
||||
# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S
|
||||
Rule Shang 1940 only - Jun 1 0:00 1:00 D
|
||||
Rule Shang 1940 only - Oct 12 24:00 0 S
|
||||
Rule Shang 1941 only - Mar 15 0:00 1:00 D
|
||||
Rule Shang 1941 only - Nov 1 24:00 0 S
|
||||
Rule Shang 1942 only - Jan 31 0:00 1:00 D
|
||||
Rule Shang 1945 only - Sep 1 24:00 0 S
|
||||
Rule Shang 1946 only - May 15 0:00 1:00 D
|
||||
Rule Shang 1946 only - Sep 30 24:00 0 S
|
||||
Rule Shang 1947 only - Apr 15 0:00 1:00 D
|
||||
Rule Shang 1947 only - Oct 31 24:00 0 S
|
||||
Rule Shang 1948 1949 - May 1 0:00 1:00 D
|
||||
Rule Shang 1948 1949 - Sep 30 24:00 0 S #plan
|
||||
|
||||
# From Guy Harris:
|
||||
# People's Republic of China. Yes, they really have only one time zone.
|
||||
|
||||
@ -330,18 +358,33 @@ Zone Asia/Yangon 6:24:47 - LMT 1880 # or Rangoon
|
||||
# time - sort of", Los Angeles Times, 1986-05-05 ... [says] that China began
|
||||
# observing daylight saving time in 1986.
|
||||
|
||||
# From Paul Eggert (2014-06-30):
|
||||
# Shanks & Pottenger have China switching to a single time zone in 1980, but
|
||||
# this doesn't seem to be correct. They also write that China observed summer
|
||||
# DST from 1986 through 1991, which seems to match the above commentary, so
|
||||
# go with them for DST rules as follows:
|
||||
# From P Chan (2018-05-07):
|
||||
# The start and end time of DST in China [from 1986 on] should be 2:00
|
||||
# (i.e. 2:00 to 3:00 at the start and 2:00 to 1:00 at the end)....
|
||||
# Government notices about summer time:
|
||||
#
|
||||
# 1986-04-12 http://www.zj.gov.cn/attach/zfgb/198608.pdf p.21-22
|
||||
# (To establish summer time from 1986. On 4 May, set the clocks ahead one hour
|
||||
# at 2 am. On 14 September, set the clocks backward one hour at 2 am.)
|
||||
#
|
||||
# 1987-02-15 http://www.gov.cn/gongbao/shuju/1987/gwyb198703.pdf p.114
|
||||
# (Summer time in 1987 to start from 12 April until 13 September)
|
||||
#
|
||||
# 1987-09-09 http://www.gov.cn/gongbao/shuju/1987/gwyb198721.pdf p.709
|
||||
# (From 1988, summer time to start from 2 am of the first Sunday of mid-April
|
||||
# until 2 am of the first Sunday of mid-September)
|
||||
#
|
||||
# 1992-03-03 http://www.gov.cn/gongbao/shuju/1992/gwyb199205.pdf p.152
|
||||
# (To suspend summer time from 1992)
|
||||
#
|
||||
# The first page of People's Daily on 12 April 1988 stating that summer time
|
||||
# to begin on 17 April.
|
||||
# http://data.people.com.cn/pic/101p/1988/04/1988041201.jpg
|
||||
|
||||
# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S
|
||||
Rule Shang 1940 only - Jun 3 0:00 1:00 D
|
||||
Rule Shang 1940 1941 - Oct 1 0:00 0 S
|
||||
Rule Shang 1941 only - Mar 16 0:00 1:00 D
|
||||
Rule PRC 1986 only - May 4 0:00 1:00 D
|
||||
Rule PRC 1986 1991 - Sep Sun>=11 0:00 0 S
|
||||
Rule PRC 1987 1991 - Apr Sun>=10 0:00 1:00 D
|
||||
Rule PRC 1986 only - May 4 2:00 1:00 D
|
||||
Rule PRC 1986 1991 - Sep Sun>=11 2:00 0 S
|
||||
Rule PRC 1987 1991 - Apr Sun>=11 2:00 1:00 D
|
||||
|
||||
# From Anthony Fok (2001-12-20):
|
||||
# BTW, I did some research on-line and found some info regarding these five
|
||||
@ -363,10 +406,11 @@ Rule PRC 1987 1991 - Apr Sun>=10 0:00 1:00 D
|
||||
# Alois Treindl kindly sent me translations of the following two sources:
|
||||
#
|
||||
# (1)
|
||||
# Guo Qingsheng (National Time-Service Center, CAS, Xi'an 710600, China)
|
||||
# Guo Qing-sheng (National Time-Service Center, CAS, Xi'an 710600, China)
|
||||
# Beijing Time at the Beginning of the PRC
|
||||
# China Historical Materials of Science and Technology
|
||||
# (Zhongguo ke ji shi liao, 中国科技史料), Vol. 24, No. 1 (2003)
|
||||
# (Zhongguo ke ji shi liao, 中国科技史料). 2003;24(1):5-9.
|
||||
# http://oversea.cnki.net/kcms/detail/detail.aspx?filename=ZGKS200301000&dbname=CJFD2003
|
||||
# It gives evidence that at the beginning of the PRC, Beijing time was
|
||||
# officially apparent solar time! However, Guo also says that the
|
||||
# evidence is dubious, as the relevant institute of astronomy had not
|
||||
@ -543,7 +587,7 @@ Rule PRC 1987 1991 - Apr Sun>=10 0:00 1:00 D
|
||||
# Zone NAME GMTOFF RULES FORMAT [UNTIL]
|
||||
# Beijing time, used throughout China; represented by Shanghai.
|
||||
Zone Asia/Shanghai 8:05:43 - LMT 1901
|
||||
8:00 Shang C%sT 1949
|
||||
8:00 Shang C%sT 1949 May 28
|
||||
8:00 PRC C%sT
|
||||
# Xinjiang time, used by many in western China; represented by Ürümqi / Ürümchi
|
||||
# / Wulumuqi. (Please use Asia/Shanghai if you prefer Beijing time.)
|
||||
@ -772,24 +816,140 @@ Zone Asia/Taipei 8:06:00 - LMT 1896 Jan 1
|
||||
8:00 Taiwan C%sT
|
||||
|
||||
# Macau (Macao, Aomen)
|
||||
#
|
||||
# From P Chan (2018-05-10):
|
||||
# * LegisMac
|
||||
# http://legismac.safp.gov.mo/legismac/descqry/Descqry.jsf?lang=pt
|
||||
# A database for searching titles of legal documents of Macau in
|
||||
# Chinese and Portuguese. The term "HORÁRIO DE VERÃO" can be used for
|
||||
# searching decrees about summer time.
|
||||
# * Archives of Macao
|
||||
# http://www.archives.gov.mo/en/bo/
|
||||
# It contains images of old official gazettes.
|
||||
# * The Macao Meteorological and Geophysical Bureau have a page listing the
|
||||
# summer time history. But it is not complete and has some mistakes.
|
||||
# http://www.smg.gov.mo/smg/geophysics/e_t_Summer%20Time.htm
|
||||
# Macau adopted GMT+8 on 30 Oct 1904 to follow Hong Kong. Clocks were
|
||||
# advanced by 25 minutes and 50 seconds. Which means the LMT used was
|
||||
# +7:34:10. As stated in the "Portaria No. 204" dated 21 October 1904
|
||||
# and published in the Official Gazette on 29 October 1904.
|
||||
# http://igallery.icm.gov.mo/Images/Archives/BO/MO_AH_PUB_BO_1904_10/MO_AH_PUB_BO_1904_10_00025_Grey.JPG
|
||||
#
|
||||
# Therefore the 1911 decree of Portugal did not change time in Macau.
|
||||
#
|
||||
# From LegisMac, here is a list of decrees that changed the time ...
|
||||
# [Decree Gazette-no. date; titles omitted in this quotation]
|
||||
# DIL 732 BOCM 51 1941.12.20
|
||||
# DIL 764 BOCM 9S 1942.04.30
|
||||
# DIL 781 BOCM 21 1942.10.10
|
||||
# PT 3434 BOCM 8S 1943.04.17
|
||||
# PT 3504 BOCM 20 1943.09.25
|
||||
# PT 3843 BOCM 39 1945.09.29
|
||||
# PT 3961 BOCM 17 1946.04.27
|
||||
# PT 4026 BOCM 39 1946.09.28
|
||||
# PT 4153 BOCM 16 1947.04.10
|
||||
# PT 4271 BOCM 48 1947.11.29
|
||||
# PT 4374 BOCM 18 1948.05.01
|
||||
# PT 4465 BOCM 44 1948.10.30
|
||||
# PT 4590 BOCM 14 1949.04.02
|
||||
# PT 4666 BOCM 44 1949.10.29
|
||||
# PT 4771 BOCM 12 1950.03.25
|
||||
# PT 4838 BOCM 43 1950.10.28
|
||||
# PT 4946 BOCM 12 1951.03.24
|
||||
# PT 5025 BO 43 1951.10.27
|
||||
# PT 5149 BO 14 1952.04.05
|
||||
# PT 5251 BO 43 1952.10.25
|
||||
# PT 5366 BO 13 1953.03.28
|
||||
# PT 5444 BO 44 1953.10.31
|
||||
# PT 5540 BO 12 1954.03.20
|
||||
# PT 5589 BO 44 1954.10.30
|
||||
# PT 5676 BO 12 1955.03.19
|
||||
# PT 5739 BO 45 1955.11.05
|
||||
# PT 5823 BO 11 1956.03.17
|
||||
# PT 5891 BO 44 1956.11.03
|
||||
# PT 5981 BO 12 1957.03.23
|
||||
# PT 6064 BO 43 1957.10.26
|
||||
# PT 6172 BO 12 1958.03.22
|
||||
# PT 6243 BO 43 1958.10.25
|
||||
# PT 6341 BO 12 1959.03.21
|
||||
# PT 6411 BO 43 1959.10.24
|
||||
# PT 6514 BO 11 1960.03.12
|
||||
# PT 6584 BO 44 1960.10.29
|
||||
# PT 6721 BO 10 1961.03.11
|
||||
# PT 6815 BO 43 1961.10.28
|
||||
# PT 6947 BO 10 1962.03.10
|
||||
# PT 7080 BO 43 1962.10.27
|
||||
# PT 7218 BO 12 1963.03.23
|
||||
# PT 7340 BO 43 1963.10.26
|
||||
# PT 7491 BO 11 1964.03.14
|
||||
# PT 7664 BO 43 1964.10.24
|
||||
# PT 7846 BO 15 1965.04.10
|
||||
# PT 7979 BO 42 1965.10.16
|
||||
# PT 8146 BO 15 1966.04.09
|
||||
# PT 8252 BO 41 1966.10.08
|
||||
# PT 8429 BO 15 1967.04.15
|
||||
# PT 8540 BO 41 1967.10.14
|
||||
# PT 8735 BO 15 1968.04.13
|
||||
# PT 8860 BO 41 1968.10.12
|
||||
# PT 9035 BO 16 1969.04.19
|
||||
# PT 9156 BO 42 1969.10.18
|
||||
# PT 9328 BO 15 1970.04.11
|
||||
# PT 9418 BO 41 1970.10.10
|
||||
# PT 9587 BO 14 1971.04.03
|
||||
# PT 9702 BO 41 1971.10.09
|
||||
# PT 38-A/72 BO 14 1972.04.01
|
||||
# PT 126-A/72 BO 41 1972.10.07
|
||||
# PT 61/73 BO 14 1973.04.07
|
||||
# PT 182/73 BO 40 1973.10.06
|
||||
# PT 282/73 BO 51 1973.12.22
|
||||
# PT 177/74 BO 41 1974.10.12
|
||||
# PT 51/75 BO 15 1975.04.12
|
||||
# PT 173/75 BO 41 1975.10.11
|
||||
# PT 67/76/M BO 14 1976.04.03
|
||||
# PT 169/76/M BO 41 1976.10.09
|
||||
# PT 78/79/M BO 19 1979.05.12
|
||||
# PT 166/79/M BO 42 1979.10.20
|
||||
# Note that DIL 732 does not belong to "HORÁRIO DE VERÃO" according to
|
||||
# LegisMac.... Note that between 1942 and 1945, the time switched
|
||||
# between GMT+9 and GMT+10. Also in 1965 and 1965 the DST ended at 2:30am.
|
||||
|
||||
# From Paul Eggert (2018-05-10):
|
||||
# The 1904 decree says that Macau changed from the meridian of
|
||||
# Fortaleza do Monte, presumably the basis for the 7:34:10 for LMT.
|
||||
|
||||
# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S
|
||||
Rule Macau 1961 1962 - Mar Sun>=16 3:30 1:00 D
|
||||
Rule Macau 1961 1964 - Nov Sun>=1 3:30 0 S
|
||||
Rule Macau 1963 only - Mar Sun>=16 0:00 1:00 D
|
||||
Rule Macau 1964 only - Mar Sun>=16 3:30 1:00 D
|
||||
Rule Macau 1965 only - Mar Sun>=16 0:00 1:00 D
|
||||
Rule Macau 1965 only - Oct 31 0:00 0 S
|
||||
Rule Macau 1966 1971 - Apr Sun>=16 3:30 1:00 D
|
||||
Rule Macau 1966 1971 - Oct Sun>=16 3:30 0 S
|
||||
Rule Macau 1972 1974 - Apr Sun>=15 0:00 1:00 D
|
||||
Rule Macau 1972 1973 - Oct Sun>=15 0:00 0 S
|
||||
Rule Macau 1974 1977 - Oct Sun>=15 3:30 0 S
|
||||
Rule Macau 1975 1977 - Apr Sun>=15 3:30 1:00 D
|
||||
Rule Macau 1978 1980 - Apr Sun>=15 0:00 1:00 D
|
||||
Rule Macau 1978 1980 - Oct Sun>=15 0:00 0 S
|
||||
# See Europe/Lisbon for info about the 1912 transition.
|
||||
Rule Macau 1942 1943 - Apr 30 23:00 1:00 -
|
||||
Rule Macau 1942 only - Nov 17 23:00 0 -
|
||||
Rule Macau 1943 only - Sep 30 23:00 0 S
|
||||
Rule Macau 1946 only - Apr 30 23:00s 1:00 D
|
||||
Rule Macau 1946 only - Sep 30 23:00s 0 S
|
||||
Rule Macau 1947 only - Apr 19 23:00s 1:00 D
|
||||
Rule Macau 1947 only - Nov 30 23:00s 0 S
|
||||
Rule Macau 1948 only - May 2 23:00s 1:00 D
|
||||
Rule Macau 1948 only - Oct 31 23:00s 0 S
|
||||
Rule Macau 1949 1950 - Apr Sat>=1 23:00s 1:00 D
|
||||
Rule Macau 1949 1950 - Oct lastSat 23:00s 0 S
|
||||
Rule Macau 1951 only - Mar 31 23:00s 1:00 D
|
||||
Rule Macau 1951 only - Oct 28 23:00s 0 S
|
||||
Rule Macau 1952 1953 - Apr Sat>=1 23:00s 1:00 D
|
||||
Rule Macau 1952 only - Nov 1 23:00s 0 S
|
||||
Rule Macau 1953 1954 - Oct lastSat 23:00s 0 S
|
||||
Rule Macau 1954 1956 - Mar Sat>=17 23:00s 1:00 D
|
||||
Rule Macau 1955 only - Nov 5 23:00s 0 S
|
||||
Rule Macau 1956 1964 - Nov Sun>=1 03:30 0 S
|
||||
Rule Macau 1957 1964 - Mar Sun>=18 03:30 1:00 D
|
||||
Rule Macau 1965 1973 - Apr Sun>=16 03:30 1:00 D
|
||||
Rule Macau 1965 1966 - Oct Sun>=16 02:30 0 S
|
||||
Rule Macau 1967 1976 - Oct Sun>=16 03:30 0 S
|
||||
Rule Macau 1973 only - Dec 30 03:30 1:00 D
|
||||
Rule Macau 1975 1976 - Apr Sun>=16 03:30 1:00 D
|
||||
Rule Macau 1979 only - May 13 03:30 1:00 D
|
||||
Rule Macau 1979 only - Oct Sun>=16 03:30 0 S
|
||||
|
||||
# Zone NAME GMTOFF RULES FORMAT [UNTIL]
|
||||
Zone Asia/Macau 7:34:20 - LMT 1911 Dec 31 16:00u
|
||||
Zone Asia/Macau 7:34:10 - LMT 1904 Oct 30
|
||||
8:00 - CST 1941 Dec 21 23:00
|
||||
9:00 Macau +09/+10 1945 Sep 30 24:00
|
||||
8:00 Macau C%sT
|
||||
|
||||
|
||||
@ -1494,9 +1654,29 @@ Zone Asia/Jerusalem 2:20:54 - LMT 1880
|
||||
# http://www.shugiin.go.jp/internet/itdb_housei.nsf/html/houritsu/00719500331039.htm
|
||||
# ... In summary, it is written as follows. From 24:00 on the first Saturday
|
||||
# in May, until 0:00 on the day after the second Saturday in September.
|
||||
|
||||
# From Phake Nick (2018-09-27):
|
||||
# [T]he webpage authored by National Astronomical Observatory of Japan
|
||||
# https://eco.mtk.nao.ac.jp/koyomi/wiki/BBFEB9EF2FB2C6BBFEB9EF.html
|
||||
# ... mentioned that using Showa 23 (year 1948) as example, 13pm of September
|
||||
# 11 in summer time will equal to 0am of September 12 in standard time.
|
||||
# It cited a document issued by the Liaison Office which briefly existed
|
||||
# during the postwar period of Japan, where the detail on implementation
|
||||
# of the summer time is described in the document.
|
||||
# https://eco.mtk.nao.ac.jp/koyomi/wiki/BBFEB9EF2FB2C6BBFEB9EFB2C6BBFEB9EFA4CEBCC2BBDCA4CBA4C4A4A4A4C6.pdf
|
||||
# The text in the document do instruct a fall back to occur at
|
||||
# September 11, 13pm in summer time, while ordinary citizens can
|
||||
# change the clock before they sleep.
|
||||
#
|
||||
# From Paul Eggert (2018-09-27):
|
||||
# This instruction is equivalent to "Sat>=8 25:00", so use that. zic treats
|
||||
# it like "Sun>=9 01:00", which is not quite the same but is the best we can
|
||||
# do in any POSIX or C platform. The "25:00" assumes zic from 2007 or later,
|
||||
# which should be safe now.
|
||||
|
||||
# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S
|
||||
Rule Japan 1948 only - May Sat>=1 24:00 1:00 D
|
||||
Rule Japan 1948 1951 - Sep Sun>=9 0:00 0 S
|
||||
Rule Japan 1948 1951 - Sep Sun>=9 1:00 0 S
|
||||
Rule Japan 1949 only - Apr Sat>=1 24:00 1:00 D
|
||||
Rule Japan 1950 1951 - May Sat>=1 24:00 1:00 D
|
||||
|
||||
@ -1878,7 +2058,7 @@ Zone Asia/Aqtobe 3:48:40 - LMT 1924 May 2
|
||||
5:00 - +05
|
||||
# Mangghystaū (KZ-MAN)
|
||||
# Aqtau was not founded until 1963, but it represents an inhabited region,
|
||||
# so include time stamps before 1963.
|
||||
# so include timestamps before 1963.
|
||||
Zone Asia/Aqtau 3:21:04 - LMT 1924 May 2
|
||||
4:00 - +04 1930 Jun 21
|
||||
5:00 - +05 1981 Oct 1
|
||||
@ -2018,6 +2198,10 @@ Rule ROK 1987 1988 - Oct Sun>=8 3:00 0 S
|
||||
# Assembly, as published in Rodong Sinmun.
|
||||
# From Tim Parenti (2018-04-29):
|
||||
# It appears to be the front page story at the top in the right-most column.
|
||||
#
|
||||
# From Paul Eggert (2018-05-04):
|
||||
# The BBC reported that the transition was from 23:30 to 24:00 today.
|
||||
# https://www.bbc.com/news/world-asia-44010705
|
||||
|
||||
# Zone NAME GMTOFF RULES FORMAT [UNTIL]
|
||||
Zone Asia/Seoul 8:27:52 - LMT 1908 Apr 1
|
||||
@ -2030,7 +2214,7 @@ Zone Asia/Pyongyang 8:23:00 - LMT 1908 Apr 1
|
||||
8:30 - KST 1912 Jan 1
|
||||
9:00 - JST 1945 Aug 24
|
||||
9:00 - KST 2015 Aug 15 00:00
|
||||
8:30 - KST 2018 May 5
|
||||
8:30 - KST 2018 May 4 23:30
|
||||
9:00 - KST
|
||||
|
||||
###############################################################################
|
||||
@ -2780,19 +2964,35 @@ Zone Asia/Hebron 2:20:23 - LMT 1900 Oct
|
||||
# Philippine Star 2014-08-05
|
||||
# http://www.philstar.com/headlines/2014/08/05/1354152/pnoy-urged-declare-use-daylight-saving-time
|
||||
|
||||
# From Paul Goyette (2018-06-15):
|
||||
# In the Philippines, there is a national law, Republic Act No. 10535
|
||||
# which declares the official time here as "Philippine Standard Time".
|
||||
# The act [1] even specifies use of PST as the abbreviation, although
|
||||
# the FAQ provided by PAGASA [2] uses the "acronym PhST to distinguish
|
||||
# it from the Pacific Standard Time (PST)."
|
||||
# [1] http://www.officialgazette.gov.ph/2013/05/15/republic-act-no-10535/
|
||||
# [2] https://www1.pagasa.dost.gov.ph/index.php/astronomy/philippine-standard-time#republic-act-10535
|
||||
#
|
||||
# From Paul Eggert (2018-06-19):
|
||||
# I surveyed recent news reports, and my impression is that "PST" is
|
||||
# more popular among reliable English-language news sources. This is
|
||||
# not just a measure of Google hit counts: it's also the sizes and
|
||||
# influence of the sources. There is no current abbreviation for DST,
|
||||
# so use "PDT", the usual American style.
|
||||
|
||||
# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S
|
||||
Rule Phil 1936 only - Nov 1 0:00 1:00 -
|
||||
Rule Phil 1937 only - Feb 1 0:00 0 -
|
||||
Rule Phil 1954 only - Apr 12 0:00 1:00 -
|
||||
Rule Phil 1954 only - Jul 1 0:00 0 -
|
||||
Rule Phil 1978 only - Mar 22 0:00 1:00 -
|
||||
Rule Phil 1978 only - Sep 21 0:00 0 -
|
||||
Rule Phil 1936 only - Nov 1 0:00 1:00 D
|
||||
Rule Phil 1937 only - Feb 1 0:00 0 S
|
||||
Rule Phil 1954 only - Apr 12 0:00 1:00 D
|
||||
Rule Phil 1954 only - Jul 1 0:00 0 S
|
||||
Rule Phil 1978 only - Mar 22 0:00 1:00 D
|
||||
Rule Phil 1978 only - Sep 21 0:00 0 S
|
||||
# Zone NAME GMTOFF RULES FORMAT [UNTIL]
|
||||
Zone Asia/Manila -15:56:00 - LMT 1844 Dec 31
|
||||
8:04:00 - LMT 1899 May 11
|
||||
8:00 Phil +08/+09 1942 May
|
||||
9:00 - +09 1944 Nov
|
||||
8:00 Phil +08/+09
|
||||
8:00 Phil P%sT 1942 May
|
||||
9:00 - JST 1944 Nov
|
||||
8:00 Phil P%sT
|
||||
|
||||
# Qatar
|
||||
# Zone NAME GMTOFF RULES FORMAT [UNTIL]
|
||||
@ -2803,15 +3003,34 @@ Link Asia/Qatar Asia/Bahrain
|
||||
|
||||
# Saudi Arabia
|
||||
#
|
||||
# From Paul Eggert (2014-07-15):
|
||||
# From Paul Eggert (2018-08-29):
|
||||
# Time in Saudi Arabia and other countries in the Arabian peninsula was not
|
||||
# standardized until relatively recently; we don't know when, and possibly it
|
||||
# standardized until 1968 or so; we don't know exactly when, and possibly it
|
||||
# has never been made official. Richard P Hunt, in "Islam city yielding to
|
||||
# modern times", New York Times (1961-04-09), p 20, wrote that only airlines
|
||||
# observed standard time, and that people in Jeddah mostly observed quasi-solar
|
||||
# time, doing so by setting their watches at sunrise to 6 o'clock (or to 12
|
||||
# o'clock for "Arab" time).
|
||||
#
|
||||
# Timekeeping differed depending on who you were and which part of Saudi
|
||||
# Arabia you were in. In 1969, Elias Antar wrote that although a common
|
||||
# practice had been to set one's watch to 12:00 (i.e., midnight) at sunset -
|
||||
# which meant that the time on one side of a mountain could differ greatly from
|
||||
# the time on the other side - many foreigners set their watches to 6pm
|
||||
# instead, while airlines instead used UTC +03 (except in Dhahran, where they
|
||||
# used UTC +04), Aramco used UTC +03 with DST, and the Trans-Arabian Pipe Line
|
||||
# Company used Aramco time in eastern Saudi Arabia and airline time in western.
|
||||
# (The American Military Aid Advisory Group used plain UTC.) Antar writes,
|
||||
# "A man named Higgins, so the story goes, used to run a local power
|
||||
# station. One day, the whole thing became too much for Higgins and he
|
||||
# assembled his staff and laid down the law. 'I've had enough of this,' he
|
||||
# shrieked. 'It is now 12 o'clock Higgins Time, and from now on this station is
|
||||
# going to run on Higgins Time.' And so, until last year, it did." See:
|
||||
# Antar E. Dinner at When? Saudi Aramco World, 1969 March/April. 2-3.
|
||||
# http://archive.aramcoworld.com/issue/196902/dinner.at.when.htm
|
||||
# newspapers.com says a similar story about Higgins was published in the Port
|
||||
# Angeles (WA) Evening News, 1965-03-10, page 5, but I lack access to the text.
|
||||
#
|
||||
# The TZ database cannot represent quasi-solar time; airline time is the best
|
||||
# we can do. The 1946 foreign air news digest of the U.S. Civil Aeronautics
|
||||
# Board (OCLC 42299995) reported that the "... Arabian Government, inaugurated
|
||||
@ -2821,7 +3040,8 @@ Link Asia/Qatar Asia/Bahrain
|
||||
#
|
||||
# Shanks & Pottenger also state that until 1968-05-01 Saudi Arabia had two
|
||||
# time zones; the other zone, at UT +04, was in the far eastern part of
|
||||
# the country. Ignore this, as it's before our 1970 cutoff.
|
||||
# the country. Presumably this is documenting airline time. Ignore this,
|
||||
# as it's before our 1970 cutoff.
|
||||
#
|
||||
# Zone NAME GMTOFF RULES FORMAT [UNTIL]
|
||||
Zone Asia/Riyadh 3:06:52 - LMT 1947 Mar 14
|
||||
|
||||
@ -21,6 +21,8 @@
|
||||
# or visit www.oracle.com if you need additional information or have any
|
||||
# questions.
|
||||
#
|
||||
# tzdb data for Australasia and environs, and for much of the Pacific
|
||||
|
||||
# This file is in the public domain, so clarified as of
|
||||
# 2009-05-17 by Arthur David Olson.
|
||||
|
||||
@ -384,8 +386,15 @@ Zone Indian/Cocos 6:27:40 - LMT 1900
|
||||
# Dominic Fok writes (2017-08-20) that DST ends 2018-01-14, citing
|
||||
# Extraordinary Government of Fiji Gazette Supplement No. 21 (2017-08-27),
|
||||
# [Legal Notice No. 41] of an order of the previous day by J Usamate.
|
||||
|
||||
# From Raymond Kumar (2018-07-13):
|
||||
# http://www.fijitimes.com/government-approves-2018-daylight-saving/
|
||||
# ... The daylight saving period will end at 3am on Sunday January 13, 2019.
|
||||
#
|
||||
# From Paul Eggert (2018-07-15):
|
||||
# For now, guess DST from 02:00 the first Sunday in November to 03:00
|
||||
# the first Sunday on or after January 14. Although ad hoc, it matches
|
||||
# the first Sunday on or after January 13. January transitions reportedly
|
||||
# depend on when school terms start. Although the guess is ad hoc, it matches
|
||||
# transitions since late 2014 and seems more likely to match future
|
||||
# practice than guessing no DST.
|
||||
|
||||
@ -399,7 +408,7 @@ Rule Fiji 2011 only - Mar Sun>=1 3:00 0 -
|
||||
Rule Fiji 2012 2013 - Jan Sun>=18 3:00 0 -
|
||||
Rule Fiji 2014 only - Jan Sun>=18 2:00 0 -
|
||||
Rule Fiji 2014 max - Nov Sun>=1 2:00 1:00 -
|
||||
Rule Fiji 2015 max - Jan Sun>=14 3:00 0 -
|
||||
Rule Fiji 2015 max - Jan Sun>=13 3:00 0 -
|
||||
# Zone NAME GMTOFF RULES FORMAT [UNTIL]
|
||||
Zone Pacific/Fiji 11:55:44 - LMT 1915 Oct 26 # Suva
|
||||
12:00 Fiji +12/+13
|
||||
|
||||
@ -21,10 +21,12 @@
|
||||
# or visit www.oracle.com if you need additional information or have any
|
||||
# questions.
|
||||
#
|
||||
# tzdb links for backward compatibility
|
||||
|
||||
# This file is in the public domain, so clarified as of
|
||||
# 2009-05-17 by Arthur David Olson.
|
||||
|
||||
# This file provides links between current names for time zones
|
||||
# This file provides links between current names for timezones
|
||||
# and their old names. Many names changed in late 1993.
|
||||
|
||||
# Link TARGET LINK-NAME
|
||||
|
||||
@ -21,12 +21,14 @@
|
||||
# or visit www.oracle.com if you need additional information or have any
|
||||
# questions.
|
||||
#
|
||||
# tzdb data for ships at sea and other miscellany
|
||||
|
||||
# This file is in the public domain, so clarified as of
|
||||
# 2009-05-17 by Arthur David Olson.
|
||||
|
||||
# These entries are mostly present for historical reasons, so that
|
||||
# people in areas not otherwise covered by the tz files could "zic -l"
|
||||
# to a time zone that was right for their area. These days, the
|
||||
# to a timezone that was right for their area. These days, the
|
||||
# tz files cover almost all the inhabited world, and the only practical
|
||||
# need now for the entries that are not on UTC are for ships at sea
|
||||
# that cannot use POSIX TZ settings.
|
||||
|
||||
@ -21,6 +21,8 @@
|
||||
# or visit www.oracle.com if you need additional information or have any
|
||||
# questions.
|
||||
#
|
||||
# tzdb data for Europe and environs
|
||||
|
||||
# This file is in the public domain, so clarified as of
|
||||
# 2009-05-17 by Arthur David Olson.
|
||||
|
||||
@ -540,7 +542,7 @@ Link Europe/London Europe/Isle_of_Man
|
||||
#
|
||||
# To work around this problem, the build procedure can translate the
|
||||
# following data into two forms, one with negative SAVE values and the
|
||||
# other form with a traditional approximation for Irish time stamps
|
||||
# other form with a traditional approximation for Irish timestamps
|
||||
# after 1971-10-31 02:00 UTC; although this approximation has tm_isdst
|
||||
# flags that are reversed, its UTC offsets are correct and this often
|
||||
# suffices. This source file currently uses only nonnegative SAVE
|
||||
@ -2450,6 +2452,33 @@ Zone Europe/Bucharest 1:44:24 - LMT 1891 Oct
|
||||
# administratively part of Sakhalin oblast', they appear to have
|
||||
# remained on UTC+11 along with Magadan.
|
||||
|
||||
# From Marat Nigametzianov (2018-07-16):
|
||||
# this is link to order from 1956 about timezone in USSR
|
||||
# http://astro.uni-altai.ru/~orion/blog/2011/11/novyie-granitsyi-chasovyih-poyasov-v-sssr/
|
||||
#
|
||||
# From Paul Eggert (2018-07-16):
|
||||
# Perhaps someone could translate the above-mentioned link and use it
|
||||
# to correct our data for the ex-Soviet Union. It cites the following:
|
||||
# «Поясное время и новые границы часовых поясов» / сост. П.Н. Долгов,
|
||||
# отв. ред. Г.Д. Бурдун - М: Комитет стандартов, мер и измерительных
|
||||
# приборов при Совете Министров СССР, Междуведомственная комиссия
|
||||
# единой службы времени, 1956 г.
|
||||
# This book looks like it would be a helpful resource for the Soviet
|
||||
# Union through 1956. Although a copy was in the Scientific Library
|
||||
# of Tomsk State University, I have not been able to track down a copy nearby.
|
||||
#
|
||||
# From Stepan Golosunov (2018-07-21):
|
||||
# http://astro.uni-altai.ru/~orion/blog/2015/05/center-reforma-ischisleniya-vremeni-br-na-territorii-sssr-v-1957-godu-center/
|
||||
# says that the 1956 decision to change time belts' borders was not
|
||||
# implemented as planned in 1956 and the change happened in 1957.
|
||||
# There is also the problem that actual time zones were different from
|
||||
# the official time belts (and from many time belts' maps) as there were
|
||||
# numerous exceptions to application of time belt rules. For example,
|
||||
# https://ru.wikipedia.org/wiki/Московское_время#Перемещение_границы_применения_московского_времени_на_восток
|
||||
# says that by 1962 there were many regions in the 3rd time belt that
|
||||
# were on Moscow time, referring to a 1962 map. By 1989 number of such
|
||||
# exceptions grew considerably.
|
||||
|
||||
# From Tim Parenti (2014-07-06):
|
||||
# The comments detailing the coverage of each Russian zone are meant to assist
|
||||
# with maintenance only and represent our best guesses as to which regions
|
||||
@ -2460,9 +2489,6 @@ Zone Europe/Bucharest 1:44:24 - LMT 1891 Oct
|
||||
# future stability. ISO 3166-2:RU codes are also listed for first-level
|
||||
# divisions where available.
|
||||
|
||||
# Zone NAME GMTOFF RULES FORMAT [UNTIL]
|
||||
|
||||
|
||||
# From Tim Parenti (2014-07-03):
|
||||
# Europe/Kaliningrad covers...
|
||||
# 39 RU-KGD Kaliningrad Oblast
|
||||
@ -2730,6 +2756,15 @@ Zone Europe/Astrakhan 3:12:12 - LMT 1924 May
|
||||
# 34 RU-VGG Volgograd Oblast
|
||||
# The 1988 transition is from USSR act No. 5 (1988-01-04).
|
||||
|
||||
# From Alexander Fetisov (2018-09-20):
|
||||
# Volgograd region in southern Russia (Europe/Volgograd) change
|
||||
# timezone from UTC+3 to UTC+4 from 28oct2018.
|
||||
# http://sozd.parliament.gov.ru/bill/452878-7
|
||||
#
|
||||
# From Stepan Golosunov (2018-10-11):
|
||||
# The law has been published today on
|
||||
# http://publication.pravo.gov.ru/Document/View/0001201810110037
|
||||
|
||||
Zone Europe/Volgograd 2:57:40 - LMT 1920 Jan 3
|
||||
3:00 - +03 1930 Jun 21
|
||||
4:00 - +04 1961 Nov 11
|
||||
@ -2738,7 +2773,8 @@ Zone Europe/Volgograd 2:57:40 - LMT 1920 Jan 3
|
||||
4:00 - +04 1992 Mar 29 2:00s
|
||||
3:00 Russia +03/+04 2011 Mar 27 2:00s
|
||||
4:00 - +04 2014 Oct 26 2:00s
|
||||
3:00 - +03
|
||||
3:00 - +03 2018 Oct 28 2:00s
|
||||
4:00 - +04
|
||||
|
||||
# From Paul Eggert (2016-11-11):
|
||||
# Europe/Saratov covers:
|
||||
@ -3427,7 +3463,8 @@ Rule Spain 1978 only - Oct 1 2:00s 0 -
|
||||
#Rule NatSpain 1937 only - May 22 23:00 1:00 S
|
||||
#Rule NatSpain 1937 1938 - Oct Sat>=1 24:00s 0 -
|
||||
#Rule NatSpain 1938 only - Mar 26 23:00 1:00 S
|
||||
# The following rules are copied from Morocco from 1967 through 1978.
|
||||
# The following rules are copied from Morocco from 1967 through 1978,
|
||||
# except with "S" letters.
|
||||
Rule SpainAfrica 1967 only - Jun 3 12:00 1:00 S
|
||||
Rule SpainAfrica 1967 only - Oct 1 0:00 0 -
|
||||
Rule SpainAfrica 1974 only - Jun 24 0:00 1:00 S
|
||||
@ -3447,6 +3484,7 @@ Zone Africa/Ceuta -0:21:16 - LMT 1900 Dec 31 23:38:44
|
||||
0:00 1:00 WEST 1918 Oct 7 23:00
|
||||
0:00 - WET 1924
|
||||
0:00 Spain WE%sT 1929
|
||||
0:00 - WET 1967 # Help zishrink.awk.
|
||||
0:00 SpainAfrica WE%sT 1984 Mar 16
|
||||
1:00 - CET 1986
|
||||
1:00 EU CE%sT
|
||||
@ -3632,7 +3670,7 @@ Zone Europe/Zurich 0:34:08 - LMT 1853 Jul 16 # See above comment.
|
||||
# http://www.resmigazete.gov.tr/eskiler/2001/03/20010324.htm#2 - for 2001
|
||||
# http://www.resmigazete.gov.tr/eskiler/2002/03/20020316.htm#2 - for 2002-2006
|
||||
# From Paul Eggert (2016-09-25):
|
||||
# Prefer the above sources to Shanks & Pottenger for time stamps after 1985.
|
||||
# Prefer the above sources to Shanks & Pottenger for timestamps after 1985.
|
||||
|
||||
# From Steffen Thorsen (2007-03-09):
|
||||
# Starting 2007 though, it seems that they are adopting EU's 1:00 UTC
|
||||
@ -3842,10 +3880,29 @@ Link Europe/Istanbul Asia/Istanbul # Istanbul is in both continents.
|
||||
# * Ukrainian Government's Resolution of 20.03.1992, No. 139.
|
||||
# http://www.uazakon.com/documents/date_8u/pg_grcasa.htm
|
||||
|
||||
# From Paul Eggert (2018-10-03):
|
||||
# As is usual in tzdb, Ukrainian zones use the most common English spellings.
|
||||
# For example, tzdb uses Europe/Kiev, as "Kiev" is the most common spelling in
|
||||
# English for Ukraine's capital, even though it is certainly wrong as a
|
||||
# transliteration of the Ukrainian "Київ". This is similar to tzdb's use of
|
||||
# Europe/Prague, which is certainly wrong as a transliteration of the Czech
|
||||
# "Praha". ("Kiev" came from old Slavic via Russian to English, and "Prague"
|
||||
# came from old Slavic via French to English, so the two cases have something
|
||||
# in common.) Admittedly English-language spelling of Ukrainian names is
|
||||
# controversial, and some day "Kyiv" may become substantially more popular in
|
||||
# English; in the meantime, stick with the traditional English "Kiev" as that
|
||||
# means less disruption for our users.
|
||||
#
|
||||
# Anyway, none of the common English-language spellings (Kiev, Kyiv, Kieff,
|
||||
# Kijeff, Kijev, Kiyef, Kiyeff) do justice to the common pronunciation in
|
||||
# Ukrainian, namely [ˈkɪjiu̯] (IPA). This pronunciation has nothing like an
|
||||
# English "v" or "f", and instead trails off with what an English-speaker
|
||||
# would call a demure "oo" sound, and it would would be better anglicized as
|
||||
# "Kuiyu". Here's a sound file, if you would like to do as the Kuiyuvians do:
|
||||
# https://commons.wikimedia.org/wiki/File:Uk-Київ.ogg
|
||||
|
||||
# Zone NAME GMTOFF RULES FORMAT [UNTIL]
|
||||
# Most of Ukraine since 1970 has been like Kiev.
|
||||
# "Kyiv" is the transliteration of the Ukrainian name, but
|
||||
# "Kiev" is more common in English.
|
||||
# This represents most of Ukraine. See above for the spelling of "Kiev".
|
||||
Zone Europe/Kiev 2:02:04 - LMT 1880
|
||||
2:02:04 - KMT 1924 May 2 # Kiev Mean Time
|
||||
2:00 - EET 1930 Jun 21
|
||||
|
||||
@ -21,11 +21,13 @@
|
||||
# or visit www.oracle.com if you need additional information or have any
|
||||
# questions.
|
||||
#
|
||||
# tzdb data for noncommittal factory settings
|
||||
|
||||
# This file is in the public domain, so clarified as of
|
||||
# 2009-05-17 by Arthur David Olson.
|
||||
|
||||
# For distributors who don't want to put time zone specification in
|
||||
# their installation procedures. Users that run 'date' will get the
|
||||
# For distributors who don't want to specify a timezone in their
|
||||
# installation procedures. Users who run 'date' will get the
|
||||
# time zone abbreviation "-00", indicating that the actual time zone
|
||||
# is unknown.
|
||||
|
||||
|
||||
@ -26,21 +26,25 @@
|
||||
# This file is in the public domain.
|
||||
|
||||
# This file is generated automatically from the data in the public-domain
|
||||
# leap-seconds.list file, which is copied from:
|
||||
# ftp://ftp.nist.gov/pub/time/leap-seconds.list
|
||||
# leap-seconds.list file, which can be copied from
|
||||
# <ftp://ftp.nist.gov/pub/time/leap-seconds.list>
|
||||
# or <ftp://ftp.boulder.nist.gov/pub/time/leap-seconds.list>
|
||||
# or <ftp://tycho.usno.navy.mil/pub/ntp/leap-seconds.list>.
|
||||
# For more about leap-seconds.list, please see
|
||||
# The NTP Timescale and Leap Seconds
|
||||
# https://www.eecis.udel.edu/~mills/leap.html
|
||||
# <https://www.eecis.udel.edu/~mills/leap.html>.
|
||||
|
||||
# The International Earth Rotation and Reference Systems Service
|
||||
# periodically uses leap seconds to keep UTC to within 0.9 s of UT1
|
||||
# (which measures the true angular orientation of the earth in space); see
|
||||
# Levine J. Coordinated Universal Time and the leap second.
|
||||
# (which measures the true angular orientation of the earth in space)
|
||||
# and publishes leap second data in a copyrighted file
|
||||
# <https://hpiers.obspm.fr/iers/bul/bulc/Leap_Second.dat>.
|
||||
# See: Levine J. Coordinated Universal Time and the leap second.
|
||||
# URSI Radio Sci Bull. 2016;89(4):30-6. doi:10.23919/URSIRSB.2016.7909995
|
||||
# http://ieeexplore.ieee.org/document/7909995/
|
||||
# <https://ieeexplore.ieee.org/document/7909995>.
|
||||
# There were no leap seconds before 1972, because the official mechanism
|
||||
# accounting for the discrepancy between atomic time and the earth's rotation
|
||||
# did not exist until the early 1970s.
|
||||
# did not exist.
|
||||
|
||||
# The correction (+ or -) is made at the given time, so lines
|
||||
# will typically look like:
|
||||
@ -48,10 +52,7 @@
|
||||
# or
|
||||
# Leap YEAR MON DAY 23:59:59 - R/S
|
||||
|
||||
# If the leapsecond is Rolling (R) the given time is local time.
|
||||
# If the leapsecond is Stationary (S) the given time is UTC.
|
||||
|
||||
# Leap YEAR MONTH DAY HH:MM:SS CORR R/S
|
||||
# If the leap second is Rolling (R) the given time is local time (unused here).
|
||||
Leap 1972 Jun 30 23:59:60 + S
|
||||
Leap 1972 Dec 31 23:59:60 + S
|
||||
Leap 1973 Dec 31 23:59:60 + S
|
||||
@ -80,5 +81,9 @@ Leap 2012 Jun 30 23:59:60 + S
|
||||
Leap 2015 Jun 30 23:59:60 + S
|
||||
Leap 2016 Dec 31 23:59:60 + S
|
||||
|
||||
# Updated through IERS Bulletin C55
|
||||
# File expires on: 28 December 2018
|
||||
# POSIX timestamps for the data in this file:
|
||||
#updated 1467936000
|
||||
#expires 1561680000
|
||||
|
||||
# Updated through IERS Bulletin C56
|
||||
# File expires on: 28 June 2019
|
||||
|
||||
@ -21,6 +21,8 @@
|
||||
# or visit www.oracle.com if you need additional information or have any
|
||||
# questions.
|
||||
#
|
||||
# tzdb data for North and Central America and environs
|
||||
|
||||
# This file is in the public domain, so clarified as of
|
||||
# 2009-05-17 by Arthur David Olson.
|
||||
|
||||
@ -71,7 +73,7 @@
|
||||
#
|
||||
# Most of the US soon followed suit. See:
|
||||
# Bartky IR. The adoption of standard time. Technol Cult 1989 Jan;30(1):25-56.
|
||||
# http://dx.doi.org/10.2307/3105430
|
||||
# https://dx.doi.org/10.2307/3105430
|
||||
|
||||
# From Paul Eggert (2005-04-16):
|
||||
# That 1883 transition occurred at 12:00 new time, not at 12:00 old time.
|
||||
@ -460,6 +462,19 @@ Zone America/North_Dakota/Beulah -6:47:07 - LMT 1883 Nov 18 12:12:53
|
||||
# western South Dakota, far western Texas (El Paso County, Hudspeth County,
|
||||
# and Pine Springs and Nickel Creek in Culberson County), Utah, Wyoming
|
||||
#
|
||||
# From Paul Eggert (2018-10-25):
|
||||
# On 1921-03-04 federal law placed all of Texas into the central time zone.
|
||||
# However, El Paso ignored the law for decades and continued to observe
|
||||
# mountain time, on the grounds that that's what they had always done
|
||||
# and they weren't about to let the federal government tell them what to do.
|
||||
# Eventually the federal government gave in and changed the law on
|
||||
# 1970-04-10 to match what El Paso was actually doing. Although
|
||||
# that's slightly after our 1970 cutoff, there is no need to create a
|
||||
# separate zone for El Paso since they were ignoring the law anyway. See:
|
||||
# Long T. El Pasoans were time rebels, fought to stay in Mountain zone.
|
||||
# El Paso Times. 2018-10-24 06:40 -06.
|
||||
# https://www.elpasotimes.com/story/news/local/el-paso/2018/10/24/el-pasoans-were-time-rebels-fought-stay-mountain-zone/1744509002/
|
||||
#
|
||||
# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER
|
||||
Rule Denver 1920 1921 - Mar lastSun 2:00 1:00 D
|
||||
Rule Denver 1920 only - Oct lastSun 2:00 0 S
|
||||
@ -729,9 +744,7 @@ Zone America/Adak 12:13:22 - LMT 1867 Oct 19 12:44:35
|
||||
Zone Pacific/Honolulu -10:31:26 - LMT 1896 Jan 13 12:00
|
||||
-10:30 - HST 1933 Apr 30 2:00
|
||||
-10:30 1:00 HDT 1933 May 21 12:00
|
||||
-10:30 - HST 1942 Feb 9 2:00
|
||||
-10:30 1:00 HDT 1945 Sep 30 2:00
|
||||
-10:30 - HST 1947 Jun 8 2:00
|
||||
-10:30 US H%sT 1947 Jun 8 2:00
|
||||
-10:00 - HST
|
||||
|
||||
# Now we turn to US areas that have diverged from the consensus since 1970.
|
||||
|
||||
@ -21,6 +21,8 @@
|
||||
# or visit www.oracle.com if you need additional information or have any
|
||||
# questions.
|
||||
#
|
||||
# tzdb data for proposed US election time (this file is obsolete)
|
||||
|
||||
# This file is in the public domain, so clarified as of
|
||||
# 2009-05-17 by Arthur David Olson.
|
||||
|
||||
|
||||
@ -21,6 +21,8 @@
|
||||
# or visit www.oracle.com if you need additional information or have any
|
||||
# questions.
|
||||
#
|
||||
# tzdb data for South America and environs
|
||||
|
||||
# This file is in the public domain, so clarified as of
|
||||
# 2009-05-17 by Arthur David Olson.
|
||||
|
||||
@ -415,7 +417,7 @@ Rule Arg 2008 only - Oct Sun>=15 0:00 1:00 -
|
||||
# standard time, so let's do that here too. This does not change UTC
|
||||
# offsets, only tm_isdst and the time zone abbreviations. One minor
|
||||
# plus is that this silences a zic complaint that there's no POSIX TZ
|
||||
# setting for time stamps past 2038.
|
||||
# setting for timestamps past 2038.
|
||||
|
||||
# Zone NAME GMTOFF RULES FORMAT [UNTIL]
|
||||
#
|
||||
@ -948,6 +950,14 @@ Rule Brazil 2016 2022 - Feb Sun>=15 0:00 0 -
|
||||
# ... https://www.timeanddate.com/news/time/brazil-delays-dst-2018.html
|
||||
# From Steffen Thorsen (2017-12-20):
|
||||
# http://www.planalto.gov.br/ccivil_03/_ato2015-2018/2017/decreto/D9242.htm
|
||||
#
|
||||
# From Fábio Gomes (2018-10-04):
|
||||
# The Brazilian president just announced a new change on this year DST.
|
||||
# It was scheduled to start on November 4th and it was changed to November 18th.
|
||||
# From Rodrigo Brüning Wessler (2018-10-15):
|
||||
# The Brazilian government just announced that the change in DST was
|
||||
# canceled.... Maybe the president Michel Temer also woke up one hour
|
||||
# earlier today. :)
|
||||
Rule Brazil 2018 max - Nov Sun>=1 0:00 1:00 -
|
||||
Rule Brazil 2023 only - Feb Sun>=22 0:00 0 -
|
||||
Rule Brazil 2024 2025 - Feb Sun>=15 0:00 0 -
|
||||
@ -1254,6 +1264,24 @@ Zone America/Rio_Branco -4:31:12 - LMT 1914
|
||||
# they will switch from -03 to -04 one hour after Santiago does that day.
|
||||
# For now, assume that they will not revert.
|
||||
|
||||
# From Juan Correa (2018-08-13):
|
||||
# As of moments ago, the Ministry of Energy in Chile has announced the new
|
||||
# schema for DST. ... Announcement in video (in Spanish):
|
||||
# https://twitter.com/MinEnergia/status/1029000399129374720
|
||||
# From Yonathan Dossow (2018-08-13):
|
||||
# The video says "first Saturday of September", we all know it means Sunday at
|
||||
# midnight.
|
||||
# From Tim Parenti (2018-08-13):
|
||||
# Translating the captions on the video at 0:44-0:55, "We want to announce as
|
||||
# Government that from 2019, Winter Time will be increased to 5 months, between
|
||||
# the first Saturday of April and the first Saturday of September."
|
||||
# At 2:08-2:20, "The Magallanes region will maintain its current time, as
|
||||
# decided by the citizens during 2017, but our Government will promote a
|
||||
# regional dialogue table to gather their opinion on this matter."
|
||||
# https://twitter.com/MinEnergia/status/1029009354001973248
|
||||
# "We will keep the new time policy unchanged for at least the next 4 years."
|
||||
# So we extend the new rules on Saturdays at 24:00 mainland time indefinitely.
|
||||
|
||||
# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S
|
||||
Rule Chile 1927 1931 - Sep 1 0:00 1:00 -
|
||||
Rule Chile 1928 1932 - Apr 1 0:00 0 -
|
||||
@ -1287,8 +1315,10 @@ Rule Chile 2011 only - May Sun>=2 3:00u 0 -
|
||||
Rule Chile 2011 only - Aug Sun>=16 4:00u 1:00 -
|
||||
Rule Chile 2012 2014 - Apr Sun>=23 3:00u 0 -
|
||||
Rule Chile 2012 2014 - Sep Sun>=2 4:00u 1:00 -
|
||||
Rule Chile 2016 max - May Sun>=9 3:00u 0 -
|
||||
Rule Chile 2016 max - Aug Sun>=9 4:00u 1:00 -
|
||||
Rule Chile 2016 2018 - May Sun>=9 3:00u 0 -
|
||||
Rule Chile 2016 2018 - Aug Sun>=9 4:00u 1:00 -
|
||||
Rule Chile 2019 max - Apr Sun>=2 3:00u 0 -
|
||||
Rule Chile 2019 max - Sep Sun>=2 4:00u 1:00 -
|
||||
# IATA SSIM anomalies: (1992-02) says 1992-03-14;
|
||||
# (1996-09) says 1998-03-08. Ignore these.
|
||||
# Zone NAME GMTOFF RULES FORMAT [UNTIL]
|
||||
|
||||
@ -21,6 +21,8 @@
|
||||
# or visit www.oracle.com if you need additional information or have any
|
||||
# questions.
|
||||
#
|
||||
# tzdb data for System V rules (this file is obsolete)
|
||||
|
||||
# This file is in the public domain, so clarified as of
|
||||
# 2009-05-17 by Arthur David Olson.
|
||||
|
||||
|
||||
@ -21,12 +21,12 @@
|
||||
# or visit www.oracle.com if you need additional information or have any
|
||||
# questions.
|
||||
#
|
||||
# tz zone descriptions (deprecated version)
|
||||
# tzdb timezone descriptions (deprecated version)
|
||||
#
|
||||
# This file is in the public domain, so clarified as of
|
||||
# 2009-05-17 by Arthur David Olson.
|
||||
#
|
||||
# From Paul Eggert (2014-07-31):
|
||||
# From Paul Eggert (2018-06-27):
|
||||
# This file is intended as a backward-compatibility aid for older programs.
|
||||
# New programs should use zone1970.tab. This file is like zone1970.tab (see
|
||||
# zone1970.tab's comments), but with the following additional restrictions:
|
||||
@ -35,13 +35,13 @@
|
||||
# 2. The first data column contains exactly one country code.
|
||||
#
|
||||
# Because of (2), each row stands for an area that is the intersection
|
||||
# of a region identified by a country code and of a zone where civil
|
||||
# of a region identified by a country code and of a timezone where civil
|
||||
# clocks have agreed since 1970; this is a narrower definition than
|
||||
# that of zone1970.tab.
|
||||
#
|
||||
# This table is intended as an aid for users, to help them select time
|
||||
# zone data entries appropriate for their practical needs. It is not
|
||||
# intended to take or endorse any position on legal or territorial claims.
|
||||
# This table is intended as an aid for users, to help them select timezones
|
||||
# appropriate for their practical needs. It is not intended to take or
|
||||
# endorse any position on legal or territorial claims.
|
||||
#
|
||||
#country-
|
||||
#code coordinates TZ comments
|
||||
@ -291,7 +291,7 @@ MM +1647+09610 Asia/Yangon
|
||||
MN +4755+10653 Asia/Ulaanbaatar Mongolia (most areas)
|
||||
MN +4801+09139 Asia/Hovd Bayan-Olgiy, Govi-Altai, Hovd, Uvs, Zavkhan
|
||||
MN +4804+11430 Asia/Choibalsan Dornod, Sukhbaatar
|
||||
MO +2214+11335 Asia/Macau
|
||||
MO +221150+1133230 Asia/Macau
|
||||
MP +1512+14545 Pacific/Saipan
|
||||
MQ +1436-06105 America/Martinique
|
||||
MR +1806-01557 Africa/Nouakchott
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
#
|
||||
# Copyright (c) 2016, Oracle and/or its affiliates. All rights reserved.
|
||||
# Copyright (c) 2016, 2018, Oracle and/or its affiliates. All rights reserved.
|
||||
# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
|
||||
#
|
||||
# This code is free software; you can redistribute it and/or modify it
|
||||
@ -67,7 +67,7 @@ PROC_SRC_DIRS := $(patsubst %, $(SRC_DIR)/%/src, $(PROC_SRC_SUBDIRS))
|
||||
|
||||
PROC_SRCS := $(filter %.java, $(call CacheFind, $(PROC_SRC_DIRS)))
|
||||
|
||||
ALL_SRC_DIRS := $(wildcard $(SRC_DIR)/*/src)
|
||||
ALL_SRC_DIRS := $(SRC_DIR) $(wildcard $(SRC_DIR)/*/src)
|
||||
SOURCEPATH := $(call PathList, $(ALL_SRC_DIRS))
|
||||
|
||||
PROCESSOR_JARS := \
|
||||
@ -81,23 +81,23 @@ PROCESSOR_PATH := $(call PathList, $(PROCESSOR_JARS))
|
||||
|
||||
ADD_EXPORTS := \
|
||||
--add-modules jdk.internal.vm.ci \
|
||||
--add-exports jdk.internal.vm.ci/jdk.vm.ci.aarch64=ALL-UNNAMED \
|
||||
--add-exports jdk.internal.vm.ci/jdk.vm.ci.amd64=ALL-UNNAMED \
|
||||
--add-exports jdk.internal.vm.ci/jdk.vm.ci.code=ALL-UNNAMED \
|
||||
--add-exports jdk.internal.vm.ci/jdk.vm.ci.code.site=ALL-UNNAMED \
|
||||
--add-exports jdk.internal.vm.ci/jdk.vm.ci.code.stack=ALL-UNNAMED \
|
||||
--add-exports jdk.internal.vm.ci/jdk.vm.ci.common=ALL-UNNAMED \
|
||||
--add-exports jdk.internal.vm.ci/jdk.vm.ci.hotspot=ALL-UNNAMED \
|
||||
--add-exports jdk.internal.vm.ci/jdk.vm.ci.hotspot.aarch64=ALL-UNNAMED \
|
||||
--add-exports jdk.internal.vm.ci/jdk.vm.ci.hotspot.amd64=ALL-UNNAMED \
|
||||
--add-exports jdk.internal.vm.ci/jdk.vm.ci.hotspot.events=ALL-UNNAMED \
|
||||
--add-exports jdk.internal.vm.ci/jdk.vm.ci.hotspot.sparc=ALL-UNNAMED \
|
||||
--add-exports jdk.internal.vm.ci/jdk.vm.ci.hotspotvmconfig=ALL-UNNAMED \
|
||||
--add-exports jdk.internal.vm.ci/jdk.vm.ci.inittimer=ALL-UNNAMED \
|
||||
--add-exports jdk.internal.vm.ci/jdk.vm.ci.meta=ALL-UNNAMED \
|
||||
--add-exports jdk.internal.vm.ci/jdk.vm.ci.runtime=ALL-UNNAMED \
|
||||
--add-exports jdk.internal.vm.ci/jdk.vm.ci.services=ALL-UNNAMED \
|
||||
--add-exports jdk.internal.vm.ci/jdk.vm.ci.sparc=ALL-UNNAMED \
|
||||
--add-exports jdk.internal.vm.ci/jdk.vm.ci.aarch64=jdk.internal.vm.compiler \
|
||||
--add-exports jdk.internal.vm.ci/jdk.vm.ci.amd64=jdk.internal.vm.compiler \
|
||||
--add-exports jdk.internal.vm.ci/jdk.vm.ci.code=jdk.internal.vm.compiler \
|
||||
--add-exports jdk.internal.vm.ci/jdk.vm.ci.code.site=jdk.internal.vm.compiler \
|
||||
--add-exports jdk.internal.vm.ci/jdk.vm.ci.code.stack=jdk.internal.vm.compiler \
|
||||
--add-exports jdk.internal.vm.ci/jdk.vm.ci.common=jdk.internal.vm.compiler \
|
||||
--add-exports jdk.internal.vm.ci/jdk.vm.ci.hotspot=jdk.internal.vm.compiler \
|
||||
--add-exports jdk.internal.vm.ci/jdk.vm.ci.hotspot.aarch64=jdk.internal.vm.compiler \
|
||||
--add-exports jdk.internal.vm.ci/jdk.vm.ci.hotspot.amd64=jdk.internal.vm.compiler \
|
||||
--add-exports jdk.internal.vm.ci/jdk.vm.ci.hotspot.events=jdk.internal.vm.compiler \
|
||||
--add-exports jdk.internal.vm.ci/jdk.vm.ci.hotspot.sparc=jdk.internal.vm.compiler \
|
||||
--add-exports jdk.internal.vm.ci/jdk.vm.ci.hotspotvmconfig=jdk.internal.vm.compiler \
|
||||
--add-exports jdk.internal.vm.ci/jdk.vm.ci.inittimer=jdk.internal.vm.compiler \
|
||||
--add-exports jdk.internal.vm.ci/jdk.vm.ci.meta=jdk.internal.vm.compiler \
|
||||
--add-exports jdk.internal.vm.ci/jdk.vm.ci.runtime=jdk.internal.vm.compiler \
|
||||
--add-exports jdk.internal.vm.ci/jdk.vm.ci.services=jdk.internal.vm.compiler \
|
||||
--add-exports jdk.internal.vm.ci/jdk.vm.ci.sparc=jdk.internal.vm.compiler \
|
||||
#
|
||||
|
||||
$(GENSRC_DIR)/_gensrc_proc_done: $(PROC_SRCS) $(PROCESSOR_JARS)
|
||||
@ -121,6 +121,7 @@ TARGETS += $(GENSRC_DIR)/_gensrc_proc_done
|
||||
################################################################################
|
||||
|
||||
$(GENSRC_DIR)/module-info.java.extra: $(GENSRC_DIR)/_gensrc_proc_done
|
||||
$(ECHO) "" > $@;
|
||||
($(CD) $(GENSRC_DIR)/META-INF/providers && \
|
||||
p=""; \
|
||||
impl=""; \
|
||||
|
||||
101
make/gensrc/Gensrc-jdk.internal.vm.compiler.management.gmk
Normal file
101
make/gensrc/Gensrc-jdk.internal.vm.compiler.management.gmk
Normal file
@ -0,0 +1,101 @@
|
||||
#
|
||||
# Copyright (c) 2016, 2018, Oracle and/or its affiliates. All rights reserved.
|
||||
# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
|
||||
#
|
||||
# This code is free software; you can redistribute it and/or modify it
|
||||
# under the terms of the GNU General Public License version 2 only, as
|
||||
# published by the Free Software Foundation. Oracle designates this
|
||||
# particular file as subject to the "Classpath" exception as provided
|
||||
# by Oracle in the LICENSE file that accompanied this code.
|
||||
#
|
||||
# This code is distributed in the hope that it will be useful, but WITHOUT
|
||||
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
# version 2 for more details (a copy is included in the LICENSE file that
|
||||
# accompanied this code).
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License version
|
||||
# 2 along with this work; if not, write to the Free Software Foundation,
|
||||
# Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
#
|
||||
# Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
|
||||
# or visit www.oracle.com if you need additional information or have any
|
||||
# questions.
|
||||
#
|
||||
|
||||
default: all
|
||||
|
||||
include $(SPEC)
|
||||
include MakeBase.gmk
|
||||
|
||||
GENSRC_DIR := $(SUPPORT_OUTPUTDIR)/gensrc/$(MODULE)
|
||||
SRC_DIR := $(TOPDIR)/src/$(MODULE)/share/classes
|
||||
|
||||
################################################################################
|
||||
|
||||
PROC_SRC_SUBDIRS := \
|
||||
org.graalvm.compiler.hotspot.management \
|
||||
#
|
||||
|
||||
PROC_SRC_DIRS := $(patsubst %, $(SRC_DIR)/%/src, $(PROC_SRC_SUBDIRS))
|
||||
|
||||
PROC_SRCS := $(filter %.java, $(call CacheFind, $(PROC_SRC_DIRS)))
|
||||
|
||||
ALL_SRC_DIRS := $(SRC_DIR) $(wildcard $(SRC_DIR)/*/src)
|
||||
SOURCEPATH := $(call PathList, $(ALL_SRC_DIRS))
|
||||
|
||||
PROCESSOR_JARS := \
|
||||
$(BUILDTOOLS_OUTPUTDIR)/jdk.vm.compiler.serviceprovider.processor.jar \
|
||||
#
|
||||
PROCESSOR_PATH := $(call PathList, $(PROCESSOR_JARS))
|
||||
|
||||
$(GENSRC_DIR)/_gensrc_proc_done: $(PROC_SRCS) $(PROCESSOR_JARS)
|
||||
$(call MakeDir, $(@D))
|
||||
$(eval $(call ListPathsSafely,PROC_SRCS,$(@D)/_gensrc_proc_files))
|
||||
$(JAVA) $(NEW_JAVAC) \
|
||||
-XDignore.symbol.file \
|
||||
--upgrade-module-path $(JDK_OUTPUTDIR)/modules --system none \
|
||||
-sourcepath $(SOURCEPATH) \
|
||||
-implicit:none \
|
||||
-proc:only \
|
||||
-processorpath $(PROCESSOR_PATH) \
|
||||
-d $(GENSRC_DIR) \
|
||||
-s $(GENSRC_DIR) \
|
||||
@$(@D)/_gensrc_proc_files
|
||||
$(TOUCH) $@
|
||||
|
||||
TARGETS += $(GENSRC_DIR)/_gensrc_proc_done
|
||||
|
||||
################################################################################
|
||||
|
||||
$(GENSRC_DIR)/module-info.java.extra: $(GENSRC_DIR)/_gensrc_proc_done
|
||||
$(ECHO) "" > $@;
|
||||
($(CD) $(GENSRC_DIR)/META-INF/providers && \
|
||||
p=""; \
|
||||
impl=""; \
|
||||
for i in $$($(GREP) '^' * | $(SORT) -t ':' -k 2 | $(SED) 's/:.*//'); do \
|
||||
c=$$($(CAT) $$i | $(TR) -d '\n\r'); \
|
||||
if test x$$p != x$$c; then \
|
||||
if test x$$p != x; then \
|
||||
$(ECHO) " ;" >> $@; \
|
||||
fi; \
|
||||
$(ECHO) "provides $$c with" >> $@; \
|
||||
p=$$c; \
|
||||
impl=""; \
|
||||
fi; \
|
||||
if test x$$impl != x; then \
|
||||
$(ECHO) " , $$i" >> $@; \
|
||||
else \
|
||||
$(ECHO) " $$i" >> $@; \
|
||||
fi; \
|
||||
impl=$$i; \
|
||||
done); \
|
||||
$(ECHO) " ;" >> $@;
|
||||
|
||||
TARGETS += $(GENSRC_DIR)/module-info.java.extra
|
||||
|
||||
################################################################################
|
||||
|
||||
all: $(TARGETS)
|
||||
|
||||
.PHONY: default all
|
||||
@ -52,7 +52,6 @@ JVM_CurrentTimeMillis
|
||||
JVM_DefineClass
|
||||
JVM_DefineClassWithSource
|
||||
JVM_DesiredAssertionStatus
|
||||
JVM_DoPrivileged
|
||||
JVM_DumpAllStacks
|
||||
JVM_DumpThreads
|
||||
JVM_FillInStackTrace
|
||||
|
||||
@ -84,7 +84,7 @@ endif
|
||||
|
||||
################################################################################
|
||||
|
||||
ifneq ($(findstring $(OPENJDK_TARGET_OS), macosx solaris aix), )
|
||||
ifneq ($(findstring $(OPENJDK_TARGET_OS), macosx solaris aix linux), )
|
||||
$(eval $(call SetupJdkExecutable, BUILD_JSPAWNHELPER, \
|
||||
NAME := jspawnhelper, \
|
||||
SRC := $(TOPDIR)/src/$(MODULE)/unix/native/jspawnhelper, \
|
||||
|
||||
@ -43,6 +43,9 @@ suite = {
|
||||
"jdk.vm.ci.services" : {
|
||||
"subDir" : "../jdk.internal.vm.ci/share/classes",
|
||||
"sourceDirs" : ["src"],
|
||||
"imports" : [
|
||||
"jdk.internal.misc"
|
||||
],
|
||||
"javaCompliance" : "9+",
|
||||
"checkstyleVersion" : "8.8",
|
||||
"workingSets" : "API,JVMCI",
|
||||
|
||||
@ -1036,7 +1036,7 @@ class HandlerImpl {
|
||||
}
|
||||
};
|
||||
|
||||
bool is_CAS(int opcode);
|
||||
bool is_CAS(int opcode, bool maybe_volatile);
|
||||
|
||||
// predicates controlling emit of ldr<x>/ldar<x> and associated dmb
|
||||
|
||||
@ -1259,12 +1259,12 @@ source %{
|
||||
// relevant dmb instructions.
|
||||
//
|
||||
|
||||
// is_CAS(int opcode)
|
||||
// is_CAS(int opcode, bool maybe_volatile)
|
||||
//
|
||||
// return true if opcode is one of the possible CompareAndSwapX
|
||||
// values otherwise false.
|
||||
|
||||
bool is_CAS(int opcode)
|
||||
bool is_CAS(int opcode, bool maybe_volatile)
|
||||
{
|
||||
switch(opcode) {
|
||||
// We handle these
|
||||
@ -1272,23 +1272,28 @@ source %{
|
||||
case Op_CompareAndSwapL:
|
||||
case Op_CompareAndSwapP:
|
||||
case Op_CompareAndSwapN:
|
||||
// case Op_CompareAndSwapB:
|
||||
// case Op_CompareAndSwapS:
|
||||
case Op_CompareAndSwapB:
|
||||
case Op_CompareAndSwapS:
|
||||
case Op_GetAndSetI:
|
||||
case Op_GetAndSetL:
|
||||
case Op_GetAndSetP:
|
||||
case Op_GetAndSetN:
|
||||
case Op_GetAndAddI:
|
||||
case Op_GetAndAddL:
|
||||
return true;
|
||||
// These are TBD
|
||||
case Op_CompareAndExchangeI:
|
||||
case Op_CompareAndExchangeN:
|
||||
case Op_CompareAndExchangeB:
|
||||
case Op_CompareAndExchangeS:
|
||||
case Op_CompareAndExchangeL:
|
||||
case Op_CompareAndExchangeP:
|
||||
case Op_WeakCompareAndSwapB:
|
||||
case Op_WeakCompareAndSwapS:
|
||||
case Op_WeakCompareAndSwapI:
|
||||
case Op_WeakCompareAndSwapL:
|
||||
case Op_WeakCompareAndSwapP:
|
||||
case Op_WeakCompareAndSwapN:
|
||||
case Op_CompareAndExchangeB:
|
||||
case Op_CompareAndExchangeS:
|
||||
case Op_CompareAndExchangeI:
|
||||
case Op_CompareAndExchangeL:
|
||||
case Op_CompareAndExchangeP:
|
||||
case Op_CompareAndExchangeN:
|
||||
return false;
|
||||
return maybe_volatile;
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
@ -1318,7 +1323,7 @@ bool unnecessary_acquire(const Node *barrier)
|
||||
if (mb->trailing_load_store()) {
|
||||
Node* load_store = mb->in(MemBarNode::Precedent);
|
||||
assert(load_store->is_LoadStore(), "unexpected graph shape");
|
||||
return is_CAS(load_store->Opcode());
|
||||
return is_CAS(load_store->Opcode(), true);
|
||||
}
|
||||
|
||||
return false;
|
||||
@ -1365,7 +1370,7 @@ bool unnecessary_release(const Node *n)
|
||||
} else {
|
||||
assert(mem->is_LoadStore(), "");
|
||||
assert(trailing_mb->Opcode() == Op_MemBarAcquire, "");
|
||||
return is_CAS(mem->Opcode());
|
||||
return is_CAS(mem->Opcode(), true);
|
||||
}
|
||||
}
|
||||
return false;
|
||||
@ -1416,13 +1421,17 @@ bool needs_releasing_store(const Node *n)
|
||||
|
||||
bool needs_acquiring_load_exclusive(const Node *n)
|
||||
{
|
||||
assert(is_CAS(n->Opcode()), "expecting a compare and swap");
|
||||
assert(is_CAS(n->Opcode(), true), "expecting a compare and swap");
|
||||
if (UseBarriersForVolatile) {
|
||||
return false;
|
||||
}
|
||||
|
||||
LoadStoreNode* ldst = n->as_LoadStore();
|
||||
assert(ldst->trailing_membar() != NULL, "expected trailing membar");
|
||||
if (is_CAS(n->Opcode(), false)) {
|
||||
assert(ldst->trailing_membar() != NULL, "expected trailing membar");
|
||||
} else {
|
||||
return ldst->trailing_membar() != NULL;
|
||||
}
|
||||
|
||||
// so we can just return true here
|
||||
return true;
|
||||
@ -2943,6 +2952,21 @@ encode %{
|
||||
/*weak*/ false, noreg);
|
||||
%}
|
||||
|
||||
enc_class aarch64_enc_cmpxchgs_acq(memory mem, iRegINoSp oldval, iRegINoSp newval) %{
|
||||
MacroAssembler _masm(&cbuf);
|
||||
guarantee($mem$$index == -1 && $mem$$disp == 0, "impossible encoding");
|
||||
__ cmpxchg($mem$$base$$Register, $oldval$$Register, $newval$$Register,
|
||||
Assembler::halfword, /*acquire*/ true, /*release*/ true,
|
||||
/*weak*/ false, noreg);
|
||||
%}
|
||||
|
||||
enc_class aarch64_enc_cmpxchgb_acq(memory mem, iRegINoSp oldval, iRegINoSp newval) %{
|
||||
MacroAssembler _masm(&cbuf);
|
||||
guarantee($mem$$index == -1 && $mem$$disp == 0, "impossible encoding");
|
||||
__ cmpxchg($mem$$base$$Register, $oldval$$Register, $newval$$Register,
|
||||
Assembler::byte, /*acquire*/ true, /*release*/ true,
|
||||
/*weak*/ false, noreg);
|
||||
%}
|
||||
|
||||
// auxiliary used for CompareAndSwapX to set result register
|
||||
enc_class aarch64_enc_cset_eq(iRegINoSp res) %{
|
||||
@ -8240,6 +8264,44 @@ instruct compareAndSwapN(iRegINoSp res, indirect mem, iRegNNoSp oldval, iRegNNoS
|
||||
|
||||
// alternative CompareAndSwapX when we are eliding barriers
|
||||
|
||||
instruct compareAndSwapBAcq(iRegINoSp res, indirect mem, iRegINoSp oldval, iRegINoSp newval, rFlagsReg cr) %{
|
||||
|
||||
predicate(needs_acquiring_load_exclusive(n));
|
||||
match(Set res (CompareAndSwapB mem (Binary oldval newval)));
|
||||
ins_cost(VOLATILE_REF_COST);
|
||||
|
||||
effect(KILL cr);
|
||||
|
||||
format %{
|
||||
"cmpxchgb_acq $mem, $oldval, $newval\t# (int) if $mem == $oldval then $mem <-- $newval"
|
||||
"cset $res, EQ\t# $res <-- (EQ ? 1 : 0)"
|
||||
%}
|
||||
|
||||
ins_encode(aarch64_enc_cmpxchgb_acq(mem, oldval, newval),
|
||||
aarch64_enc_cset_eq(res));
|
||||
|
||||
ins_pipe(pipe_slow);
|
||||
%}
|
||||
|
||||
instruct compareAndSwapSAcq(iRegINoSp res, indirect mem, iRegINoSp oldval, iRegINoSp newval, rFlagsReg cr) %{
|
||||
|
||||
predicate(needs_acquiring_load_exclusive(n));
|
||||
match(Set res (CompareAndSwapS mem (Binary oldval newval)));
|
||||
ins_cost(VOLATILE_REF_COST);
|
||||
|
||||
effect(KILL cr);
|
||||
|
||||
format %{
|
||||
"cmpxchgs_acq $mem, $oldval, $newval\t# (int) if $mem == $oldval then $mem <-- $newval"
|
||||
"cset $res, EQ\t# $res <-- (EQ ? 1 : 0)"
|
||||
%}
|
||||
|
||||
ins_encode(aarch64_enc_cmpxchgs_acq(mem, oldval, newval),
|
||||
aarch64_enc_cset_eq(res));
|
||||
|
||||
ins_pipe(pipe_slow);
|
||||
%}
|
||||
|
||||
instruct compareAndSwapIAcq(iRegINoSp res, indirect mem, iRegINoSp oldval, iRegINoSp newval, rFlagsReg cr) %{
|
||||
|
||||
predicate(needs_acquiring_load_exclusive(n));
|
||||
@ -8338,11 +8400,10 @@ instruct compareAndExchangeB(iRegINoSp res, indirect mem, iRegI oldval, iRegI ne
|
||||
ins_cost(2 * VOLATILE_REF_COST);
|
||||
effect(TEMP_DEF res, KILL cr);
|
||||
format %{
|
||||
"cmpxchg $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval"
|
||||
"cmpxchgb $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval"
|
||||
%}
|
||||
ins_encode %{
|
||||
__ uxtbw(rscratch2, $oldval$$Register);
|
||||
__ cmpxchg($mem$$Register, rscratch2, $newval$$Register,
|
||||
__ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
|
||||
Assembler::byte, /*acquire*/ false, /*release*/ true,
|
||||
/*weak*/ false, $res$$Register);
|
||||
__ sxtbw($res$$Register, $res$$Register);
|
||||
@ -8355,11 +8416,10 @@ instruct compareAndExchangeS(iRegINoSp res, indirect mem, iRegI oldval, iRegI ne
|
||||
ins_cost(2 * VOLATILE_REF_COST);
|
||||
effect(TEMP_DEF res, KILL cr);
|
||||
format %{
|
||||
"cmpxchg $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval"
|
||||
"cmpxchgs $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval"
|
||||
%}
|
||||
ins_encode %{
|
||||
__ uxthw(rscratch2, $oldval$$Register);
|
||||
__ cmpxchg($mem$$Register, rscratch2, $newval$$Register,
|
||||
__ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
|
||||
Assembler::halfword, /*acquire*/ false, /*release*/ true,
|
||||
/*weak*/ false, $res$$Register);
|
||||
__ sxthw($res$$Register, $res$$Register);
|
||||
@ -8372,7 +8432,7 @@ instruct compareAndExchangeI(iRegINoSp res, indirect mem, iRegI oldval, iRegI ne
|
||||
ins_cost(2 * VOLATILE_REF_COST);
|
||||
effect(TEMP_DEF res, KILL cr);
|
||||
format %{
|
||||
"cmpxchg $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval"
|
||||
"cmpxchgw $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval"
|
||||
%}
|
||||
ins_encode %{
|
||||
__ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
|
||||
@ -8402,7 +8462,7 @@ instruct compareAndExchangeN(iRegNNoSp res, indirect mem, iRegN oldval, iRegN ne
|
||||
ins_cost(2 * VOLATILE_REF_COST);
|
||||
effect(TEMP_DEF res, KILL cr);
|
||||
format %{
|
||||
"cmpxchg $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval"
|
||||
"cmpxchgw $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval"
|
||||
%}
|
||||
ins_encode %{
|
||||
__ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
|
||||
@ -8427,17 +8487,116 @@ instruct compareAndExchangeP(iRegPNoSp res, indirect mem, iRegP oldval, iRegP ne
|
||||
ins_pipe(pipe_slow);
|
||||
%}
|
||||
|
||||
instruct compareAndExchangeBAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval, rFlagsReg cr) %{
|
||||
predicate(needs_acquiring_load_exclusive(n));
|
||||
match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
|
||||
ins_cost(VOLATILE_REF_COST);
|
||||
effect(TEMP_DEF res, KILL cr);
|
||||
format %{
|
||||
"cmpxchgb_acq $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval"
|
||||
%}
|
||||
ins_encode %{
|
||||
__ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
|
||||
Assembler::byte, /*acquire*/ true, /*release*/ true,
|
||||
/*weak*/ false, $res$$Register);
|
||||
__ sxtbw($res$$Register, $res$$Register);
|
||||
%}
|
||||
ins_pipe(pipe_slow);
|
||||
%}
|
||||
|
||||
instruct compareAndExchangeSAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval, rFlagsReg cr) %{
|
||||
predicate(needs_acquiring_load_exclusive(n));
|
||||
match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
|
||||
ins_cost(VOLATILE_REF_COST);
|
||||
effect(TEMP_DEF res, KILL cr);
|
||||
format %{
|
||||
"cmpxchgs_acq $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval"
|
||||
%}
|
||||
ins_encode %{
|
||||
__ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
|
||||
Assembler::halfword, /*acquire*/ true, /*release*/ true,
|
||||
/*weak*/ false, $res$$Register);
|
||||
__ sxthw($res$$Register, $res$$Register);
|
||||
%}
|
||||
ins_pipe(pipe_slow);
|
||||
%}
|
||||
|
||||
|
||||
instruct compareAndExchangeIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval, rFlagsReg cr) %{
|
||||
predicate(needs_acquiring_load_exclusive(n));
|
||||
match(Set res (CompareAndExchangeI mem (Binary oldval newval)));
|
||||
ins_cost(VOLATILE_REF_COST);
|
||||
effect(TEMP_DEF res, KILL cr);
|
||||
format %{
|
||||
"cmpxchgw_acq $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval"
|
||||
%}
|
||||
ins_encode %{
|
||||
__ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
|
||||
Assembler::word, /*acquire*/ true, /*release*/ true,
|
||||
/*weak*/ false, $res$$Register);
|
||||
%}
|
||||
ins_pipe(pipe_slow);
|
||||
%}
|
||||
|
||||
instruct compareAndExchangeLAcq(iRegLNoSp res, indirect mem, iRegL oldval, iRegL newval, rFlagsReg cr) %{
|
||||
predicate(needs_acquiring_load_exclusive(n));
|
||||
match(Set res (CompareAndExchangeL mem (Binary oldval newval)));
|
||||
ins_cost(VOLATILE_REF_COST);
|
||||
effect(TEMP_DEF res, KILL cr);
|
||||
format %{
|
||||
"cmpxchg_acq $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval"
|
||||
%}
|
||||
ins_encode %{
|
||||
__ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
|
||||
Assembler::xword, /*acquire*/ true, /*release*/ true,
|
||||
/*weak*/ false, $res$$Register);
|
||||
%}
|
||||
ins_pipe(pipe_slow);
|
||||
%}
|
||||
|
||||
|
||||
instruct compareAndExchangeNAcq(iRegNNoSp res, indirect mem, iRegN oldval, iRegN newval, rFlagsReg cr) %{
|
||||
predicate(needs_acquiring_load_exclusive(n));
|
||||
match(Set res (CompareAndExchangeN mem (Binary oldval newval)));
|
||||
ins_cost(VOLATILE_REF_COST);
|
||||
effect(TEMP_DEF res, KILL cr);
|
||||
format %{
|
||||
"cmpxchgw_acq $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval"
|
||||
%}
|
||||
ins_encode %{
|
||||
__ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
|
||||
Assembler::word, /*acquire*/ true, /*release*/ true,
|
||||
/*weak*/ false, $res$$Register);
|
||||
%}
|
||||
ins_pipe(pipe_slow);
|
||||
%}
|
||||
|
||||
instruct compareAndExchangePAcq(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval, rFlagsReg cr) %{
|
||||
predicate(needs_acquiring_load_exclusive(n));
|
||||
match(Set res (CompareAndExchangeP mem (Binary oldval newval)));
|
||||
ins_cost(VOLATILE_REF_COST);
|
||||
effect(TEMP_DEF res, KILL cr);
|
||||
format %{
|
||||
"cmpxchg_acq $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval"
|
||||
%}
|
||||
ins_encode %{
|
||||
__ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
|
||||
Assembler::xword, /*acquire*/ true, /*release*/ true,
|
||||
/*weak*/ false, $res$$Register);
|
||||
%}
|
||||
ins_pipe(pipe_slow);
|
||||
%}
|
||||
|
||||
instruct weakCompareAndSwapB(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval, rFlagsReg cr) %{
|
||||
match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
|
||||
ins_cost(2 * VOLATILE_REF_COST);
|
||||
effect(KILL cr);
|
||||
format %{
|
||||
"cmpxchg $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval"
|
||||
"cmpxchgb $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval"
|
||||
"csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)"
|
||||
%}
|
||||
ins_encode %{
|
||||
__ uxtbw(rscratch2, $oldval$$Register);
|
||||
__ cmpxchg($mem$$Register, rscratch2, $newval$$Register,
|
||||
__ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
|
||||
Assembler::byte, /*acquire*/ false, /*release*/ true,
|
||||
/*weak*/ true, noreg);
|
||||
__ csetw($res$$Register, Assembler::EQ);
|
||||
@ -8450,12 +8609,11 @@ instruct weakCompareAndSwapS(iRegINoSp res, indirect mem, iRegI oldval, iRegI ne
|
||||
ins_cost(2 * VOLATILE_REF_COST);
|
||||
effect(KILL cr);
|
||||
format %{
|
||||
"cmpxchg $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval"
|
||||
"cmpxchgs $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval"
|
||||
"csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)"
|
||||
%}
|
||||
ins_encode %{
|
||||
__ uxthw(rscratch2, $oldval$$Register);
|
||||
__ cmpxchg($mem$$Register, rscratch2, $newval$$Register,
|
||||
__ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
|
||||
Assembler::halfword, /*acquire*/ false, /*release*/ true,
|
||||
/*weak*/ true, noreg);
|
||||
__ csetw($res$$Register, Assembler::EQ);
|
||||
@ -8468,7 +8626,7 @@ instruct weakCompareAndSwapI(iRegINoSp res, indirect mem, iRegI oldval, iRegI ne
|
||||
ins_cost(2 * VOLATILE_REF_COST);
|
||||
effect(KILL cr);
|
||||
format %{
|
||||
"cmpxchg $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval"
|
||||
"cmpxchgw $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval"
|
||||
"csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)"
|
||||
%}
|
||||
ins_encode %{
|
||||
@ -8502,7 +8660,7 @@ instruct weakCompareAndSwapN(iRegINoSp res, indirect mem, iRegN oldval, iRegN ne
|
||||
ins_cost(2 * VOLATILE_REF_COST);
|
||||
effect(KILL cr);
|
||||
format %{
|
||||
"cmpxchg $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval"
|
||||
"cmpxchgw $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval"
|
||||
"csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)"
|
||||
%}
|
||||
ins_encode %{
|
||||
@ -8531,11 +8689,120 @@ instruct weakCompareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP ne
|
||||
ins_pipe(pipe_slow);
|
||||
%}
|
||||
|
||||
instruct weakCompareAndSwapBAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval, rFlagsReg cr) %{
|
||||
predicate(needs_acquiring_load_exclusive(n));
|
||||
match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
|
||||
ins_cost(VOLATILE_REF_COST);
|
||||
effect(KILL cr);
|
||||
format %{
|
||||
"cmpxchgb_acq $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval"
|
||||
"csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)"
|
||||
%}
|
||||
ins_encode %{
|
||||
__ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
|
||||
Assembler::byte, /*acquire*/ true, /*release*/ true,
|
||||
/*weak*/ true, noreg);
|
||||
__ csetw($res$$Register, Assembler::EQ);
|
||||
%}
|
||||
ins_pipe(pipe_slow);
|
||||
%}
|
||||
|
||||
instruct weakCompareAndSwapSAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval, rFlagsReg cr) %{
|
||||
predicate(needs_acquiring_load_exclusive(n));
|
||||
match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
|
||||
ins_cost(VOLATILE_REF_COST);
|
||||
effect(KILL cr);
|
||||
format %{
|
||||
"cmpxchgs_acq $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval"
|
||||
"csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)"
|
||||
%}
|
||||
ins_encode %{
|
||||
__ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
|
||||
Assembler::halfword, /*acquire*/ true, /*release*/ true,
|
||||
/*weak*/ true, noreg);
|
||||
__ csetw($res$$Register, Assembler::EQ);
|
||||
%}
|
||||
ins_pipe(pipe_slow);
|
||||
%}
|
||||
|
||||
instruct weakCompareAndSwapIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval, rFlagsReg cr) %{
|
||||
predicate(needs_acquiring_load_exclusive(n));
|
||||
match(Set res (WeakCompareAndSwapI mem (Binary oldval newval)));
|
||||
ins_cost(VOLATILE_REF_COST);
|
||||
effect(KILL cr);
|
||||
format %{
|
||||
"cmpxchgw_acq $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval"
|
||||
"csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)"
|
||||
%}
|
||||
ins_encode %{
|
||||
__ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
|
||||
Assembler::word, /*acquire*/ true, /*release*/ true,
|
||||
/*weak*/ true, noreg);
|
||||
__ csetw($res$$Register, Assembler::EQ);
|
||||
%}
|
||||
ins_pipe(pipe_slow);
|
||||
%}
|
||||
|
||||
instruct weakCompareAndSwapLAcq(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval, rFlagsReg cr) %{
|
||||
predicate(needs_acquiring_load_exclusive(n));
|
||||
match(Set res (WeakCompareAndSwapL mem (Binary oldval newval)));
|
||||
ins_cost(VOLATILE_REF_COST);
|
||||
effect(KILL cr);
|
||||
format %{
|
||||
"cmpxchg_acq $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval"
|
||||
"csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)"
|
||||
%}
|
||||
ins_encode %{
|
||||
__ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
|
||||
Assembler::xword, /*acquire*/ true, /*release*/ true,
|
||||
/*weak*/ true, noreg);
|
||||
__ csetw($res$$Register, Assembler::EQ);
|
||||
%}
|
||||
ins_pipe(pipe_slow);
|
||||
%}
|
||||
|
||||
instruct weakCompareAndSwapNAcq(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval, rFlagsReg cr) %{
|
||||
predicate(needs_acquiring_load_exclusive(n));
|
||||
match(Set res (WeakCompareAndSwapN mem (Binary oldval newval)));
|
||||
ins_cost(VOLATILE_REF_COST);
|
||||
effect(KILL cr);
|
||||
format %{
|
||||
"cmpxchgw_acq $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval"
|
||||
"csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)"
|
||||
%}
|
||||
ins_encode %{
|
||||
__ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
|
||||
Assembler::word, /*acquire*/ true, /*release*/ true,
|
||||
/*weak*/ true, noreg);
|
||||
__ csetw($res$$Register, Assembler::EQ);
|
||||
%}
|
||||
ins_pipe(pipe_slow);
|
||||
%}
|
||||
|
||||
instruct weakCompareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval, rFlagsReg cr) %{
|
||||
predicate(needs_acquiring_load_exclusive(n));
|
||||
match(Set res (WeakCompareAndSwapP mem (Binary oldval newval)));
|
||||
ins_cost(VOLATILE_REF_COST);
|
||||
effect(KILL cr);
|
||||
format %{
|
||||
"cmpxchg_acq $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval"
|
||||
"csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)"
|
||||
%}
|
||||
ins_encode %{
|
||||
__ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
|
||||
Assembler::xword, /*acquire*/ true, /*release*/ true,
|
||||
/*weak*/ true, noreg);
|
||||
__ csetw($res$$Register, Assembler::EQ);
|
||||
%}
|
||||
ins_pipe(pipe_slow);
|
||||
%}
|
||||
|
||||
// END This section of the file is automatically generated. Do not edit --------------
|
||||
// ---------------------------------------------------------------------
|
||||
|
||||
instruct get_and_setI(indirect mem, iRegI newv, iRegINoSp prev) %{
|
||||
match(Set prev (GetAndSetI mem newv));
|
||||
ins_cost(2 * VOLATILE_REF_COST);
|
||||
format %{ "atomic_xchgw $prev, $newv, [$mem]" %}
|
||||
ins_encode %{
|
||||
__ atomic_xchgw($prev$$Register, $newv$$Register, as_Register($mem$$base));
|
||||
@ -8545,6 +8812,7 @@ instruct get_and_setI(indirect mem, iRegI newv, iRegINoSp prev) %{
|
||||
|
||||
instruct get_and_setL(indirect mem, iRegL newv, iRegLNoSp prev) %{
|
||||
match(Set prev (GetAndSetL mem newv));
|
||||
ins_cost(2 * VOLATILE_REF_COST);
|
||||
format %{ "atomic_xchg $prev, $newv, [$mem]" %}
|
||||
ins_encode %{
|
||||
__ atomic_xchg($prev$$Register, $newv$$Register, as_Register($mem$$base));
|
||||
@ -8554,6 +8822,7 @@ instruct get_and_setL(indirect mem, iRegL newv, iRegLNoSp prev) %{
|
||||
|
||||
instruct get_and_setN(indirect mem, iRegN newv, iRegINoSp prev) %{
|
||||
match(Set prev (GetAndSetN mem newv));
|
||||
ins_cost(2 * VOLATILE_REF_COST);
|
||||
format %{ "atomic_xchgw $prev, $newv, [$mem]" %}
|
||||
ins_encode %{
|
||||
__ atomic_xchgw($prev$$Register, $newv$$Register, as_Register($mem$$base));
|
||||
@ -8563,6 +8832,7 @@ instruct get_and_setN(indirect mem, iRegN newv, iRegINoSp prev) %{
|
||||
|
||||
instruct get_and_setP(indirect mem, iRegP newv, iRegPNoSp prev) %{
|
||||
match(Set prev (GetAndSetP mem newv));
|
||||
ins_cost(2 * VOLATILE_REF_COST);
|
||||
format %{ "atomic_xchg $prev, $newv, [$mem]" %}
|
||||
ins_encode %{
|
||||
__ atomic_xchg($prev$$Register, $newv$$Register, as_Register($mem$$base));
|
||||
@ -8570,10 +8840,54 @@ instruct get_and_setP(indirect mem, iRegP newv, iRegPNoSp prev) %{
|
||||
ins_pipe(pipe_serial);
|
||||
%}
|
||||
|
||||
instruct get_and_setIAcq(indirect mem, iRegI newv, iRegINoSp prev) %{
|
||||
predicate(needs_acquiring_load_exclusive(n));
|
||||
match(Set prev (GetAndSetI mem newv));
|
||||
ins_cost(VOLATILE_REF_COST);
|
||||
format %{ "atomic_xchgw_acq $prev, $newv, [$mem]" %}
|
||||
ins_encode %{
|
||||
__ atomic_xchgalw($prev$$Register, $newv$$Register, as_Register($mem$$base));
|
||||
%}
|
||||
ins_pipe(pipe_serial);
|
||||
%}
|
||||
|
||||
instruct get_and_setLAcq(indirect mem, iRegL newv, iRegLNoSp prev) %{
|
||||
predicate(needs_acquiring_load_exclusive(n));
|
||||
match(Set prev (GetAndSetL mem newv));
|
||||
ins_cost(VOLATILE_REF_COST);
|
||||
format %{ "atomic_xchg_acq $prev, $newv, [$mem]" %}
|
||||
ins_encode %{
|
||||
__ atomic_xchgal($prev$$Register, $newv$$Register, as_Register($mem$$base));
|
||||
%}
|
||||
ins_pipe(pipe_serial);
|
||||
%}
|
||||
|
||||
instruct get_and_setNAcq(indirect mem, iRegN newv, iRegINoSp prev) %{
|
||||
predicate(needs_acquiring_load_exclusive(n));
|
||||
match(Set prev (GetAndSetN mem newv));
|
||||
ins_cost(VOLATILE_REF_COST);
|
||||
format %{ "atomic_xchgw_acq $prev, $newv, [$mem]" %}
|
||||
ins_encode %{
|
||||
__ atomic_xchgalw($prev$$Register, $newv$$Register, as_Register($mem$$base));
|
||||
%}
|
||||
ins_pipe(pipe_serial);
|
||||
%}
|
||||
|
||||
instruct get_and_setPAcq(indirect mem, iRegP newv, iRegPNoSp prev) %{
|
||||
predicate(needs_acquiring_load_exclusive(n));
|
||||
match(Set prev (GetAndSetP mem newv));
|
||||
ins_cost(VOLATILE_REF_COST);
|
||||
format %{ "atomic_xchg_acq $prev, $newv, [$mem]" %}
|
||||
ins_encode %{
|
||||
__ atomic_xchgal($prev$$Register, $newv$$Register, as_Register($mem$$base));
|
||||
%}
|
||||
ins_pipe(pipe_serial);
|
||||
%}
|
||||
|
||||
|
||||
instruct get_and_addL(indirect mem, iRegLNoSp newval, iRegL incr) %{
|
||||
match(Set newval (GetAndAddL mem incr));
|
||||
ins_cost(INSN_COST * 10);
|
||||
ins_cost(2 * VOLATILE_REF_COST + 1);
|
||||
format %{ "get_and_addL $newval, [$mem], $incr" %}
|
||||
ins_encode %{
|
||||
__ atomic_add($newval$$Register, $incr$$Register, as_Register($mem$$base));
|
||||
@ -8584,7 +8898,7 @@ instruct get_and_addL(indirect mem, iRegLNoSp newval, iRegL incr) %{
|
||||
instruct get_and_addL_no_res(indirect mem, Universe dummy, iRegL incr) %{
|
||||
predicate(n->as_LoadStore()->result_not_used());
|
||||
match(Set dummy (GetAndAddL mem incr));
|
||||
ins_cost(INSN_COST * 9);
|
||||
ins_cost(2 * VOLATILE_REF_COST);
|
||||
format %{ "get_and_addL [$mem], $incr" %}
|
||||
ins_encode %{
|
||||
__ atomic_add(noreg, $incr$$Register, as_Register($mem$$base));
|
||||
@ -8594,7 +8908,7 @@ instruct get_and_addL_no_res(indirect mem, Universe dummy, iRegL incr) %{
|
||||
|
||||
instruct get_and_addLi(indirect mem, iRegLNoSp newval, immLAddSub incr) %{
|
||||
match(Set newval (GetAndAddL mem incr));
|
||||
ins_cost(INSN_COST * 10);
|
||||
ins_cost(2 * VOLATILE_REF_COST + 1);
|
||||
format %{ "get_and_addL $newval, [$mem], $incr" %}
|
||||
ins_encode %{
|
||||
__ atomic_add($newval$$Register, $incr$$constant, as_Register($mem$$base));
|
||||
@ -8605,7 +8919,7 @@ instruct get_and_addLi(indirect mem, iRegLNoSp newval, immLAddSub incr) %{
|
||||
instruct get_and_addLi_no_res(indirect mem, Universe dummy, immLAddSub incr) %{
|
||||
predicate(n->as_LoadStore()->result_not_used());
|
||||
match(Set dummy (GetAndAddL mem incr));
|
||||
ins_cost(INSN_COST * 9);
|
||||
ins_cost(2 * VOLATILE_REF_COST);
|
||||
format %{ "get_and_addL [$mem], $incr" %}
|
||||
ins_encode %{
|
||||
__ atomic_add(noreg, $incr$$constant, as_Register($mem$$base));
|
||||
@ -8615,7 +8929,7 @@ instruct get_and_addLi_no_res(indirect mem, Universe dummy, immLAddSub incr) %{
|
||||
|
||||
instruct get_and_addI(indirect mem, iRegINoSp newval, iRegIorL2I incr) %{
|
||||
match(Set newval (GetAndAddI mem incr));
|
||||
ins_cost(INSN_COST * 10);
|
||||
ins_cost(2 * VOLATILE_REF_COST + 1);
|
||||
format %{ "get_and_addI $newval, [$mem], $incr" %}
|
||||
ins_encode %{
|
||||
__ atomic_addw($newval$$Register, $incr$$Register, as_Register($mem$$base));
|
||||
@ -8626,7 +8940,7 @@ instruct get_and_addI(indirect mem, iRegINoSp newval, iRegIorL2I incr) %{
|
||||
instruct get_and_addI_no_res(indirect mem, Universe dummy, iRegIorL2I incr) %{
|
||||
predicate(n->as_LoadStore()->result_not_used());
|
||||
match(Set dummy (GetAndAddI mem incr));
|
||||
ins_cost(INSN_COST * 9);
|
||||
ins_cost(2 * VOLATILE_REF_COST);
|
||||
format %{ "get_and_addI [$mem], $incr" %}
|
||||
ins_encode %{
|
||||
__ atomic_addw(noreg, $incr$$Register, as_Register($mem$$base));
|
||||
@ -8636,7 +8950,7 @@ instruct get_and_addI_no_res(indirect mem, Universe dummy, iRegIorL2I incr) %{
|
||||
|
||||
instruct get_and_addIi(indirect mem, iRegINoSp newval, immIAddSub incr) %{
|
||||
match(Set newval (GetAndAddI mem incr));
|
||||
ins_cost(INSN_COST * 10);
|
||||
ins_cost(2 * VOLATILE_REF_COST + 1);
|
||||
format %{ "get_and_addI $newval, [$mem], $incr" %}
|
||||
ins_encode %{
|
||||
__ atomic_addw($newval$$Register, $incr$$constant, as_Register($mem$$base));
|
||||
@ -8647,7 +8961,7 @@ instruct get_and_addIi(indirect mem, iRegINoSp newval, immIAddSub incr) %{
|
||||
instruct get_and_addIi_no_res(indirect mem, Universe dummy, immIAddSub incr) %{
|
||||
predicate(n->as_LoadStore()->result_not_used());
|
||||
match(Set dummy (GetAndAddI mem incr));
|
||||
ins_cost(INSN_COST * 9);
|
||||
ins_cost(2 * VOLATILE_REF_COST);
|
||||
format %{ "get_and_addI [$mem], $incr" %}
|
||||
ins_encode %{
|
||||
__ atomic_addw(noreg, $incr$$constant, as_Register($mem$$base));
|
||||
@ -8655,6 +8969,94 @@ instruct get_and_addIi_no_res(indirect mem, Universe dummy, immIAddSub incr) %{
|
||||
ins_pipe(pipe_serial);
|
||||
%}
|
||||
|
||||
instruct get_and_addLAcq(indirect mem, iRegLNoSp newval, iRegL incr) %{
|
||||
predicate(needs_acquiring_load_exclusive(n));
|
||||
match(Set newval (GetAndAddL mem incr));
|
||||
ins_cost(VOLATILE_REF_COST + 1);
|
||||
format %{ "get_and_addL_acq $newval, [$mem], $incr" %}
|
||||
ins_encode %{
|
||||
__ atomic_addal($newval$$Register, $incr$$Register, as_Register($mem$$base));
|
||||
%}
|
||||
ins_pipe(pipe_serial);
|
||||
%}
|
||||
|
||||
instruct get_and_addL_no_resAcq(indirect mem, Universe dummy, iRegL incr) %{
|
||||
predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_exclusive(n));
|
||||
match(Set dummy (GetAndAddL mem incr));
|
||||
ins_cost(VOLATILE_REF_COST);
|
||||
format %{ "get_and_addL_acq [$mem], $incr" %}
|
||||
ins_encode %{
|
||||
__ atomic_addal(noreg, $incr$$Register, as_Register($mem$$base));
|
||||
%}
|
||||
ins_pipe(pipe_serial);
|
||||
%}
|
||||
|
||||
instruct get_and_addLiAcq(indirect mem, iRegLNoSp newval, immLAddSub incr) %{
|
||||
predicate(needs_acquiring_load_exclusive(n));
|
||||
match(Set newval (GetAndAddL mem incr));
|
||||
ins_cost(VOLATILE_REF_COST + 1);
|
||||
format %{ "get_and_addL_acq $newval, [$mem], $incr" %}
|
||||
ins_encode %{
|
||||
__ atomic_addal($newval$$Register, $incr$$constant, as_Register($mem$$base));
|
||||
%}
|
||||
ins_pipe(pipe_serial);
|
||||
%}
|
||||
|
||||
instruct get_and_addLi_no_resAcq(indirect mem, Universe dummy, immLAddSub incr) %{
|
||||
predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_exclusive(n));
|
||||
match(Set dummy (GetAndAddL mem incr));
|
||||
ins_cost(VOLATILE_REF_COST);
|
||||
format %{ "get_and_addL_acq [$mem], $incr" %}
|
||||
ins_encode %{
|
||||
__ atomic_addal(noreg, $incr$$constant, as_Register($mem$$base));
|
||||
%}
|
||||
ins_pipe(pipe_serial);
|
||||
%}
|
||||
|
||||
instruct get_and_addIAcq(indirect mem, iRegINoSp newval, iRegIorL2I incr) %{
|
||||
predicate(needs_acquiring_load_exclusive(n));
|
||||
match(Set newval (GetAndAddI mem incr));
|
||||
ins_cost(VOLATILE_REF_COST + 1);
|
||||
format %{ "get_and_addI_acq $newval, [$mem], $incr" %}
|
||||
ins_encode %{
|
||||
__ atomic_addalw($newval$$Register, $incr$$Register, as_Register($mem$$base));
|
||||
%}
|
||||
ins_pipe(pipe_serial);
|
||||
%}
|
||||
|
||||
instruct get_and_addI_no_resAcq(indirect mem, Universe dummy, iRegIorL2I incr) %{
|
||||
predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_exclusive(n));
|
||||
match(Set dummy (GetAndAddI mem incr));
|
||||
ins_cost(VOLATILE_REF_COST);
|
||||
format %{ "get_and_addI_acq [$mem], $incr" %}
|
||||
ins_encode %{
|
||||
__ atomic_addalw(noreg, $incr$$Register, as_Register($mem$$base));
|
||||
%}
|
||||
ins_pipe(pipe_serial);
|
||||
%}
|
||||
|
||||
instruct get_and_addIiAcq(indirect mem, iRegINoSp newval, immIAddSub incr) %{
|
||||
predicate(needs_acquiring_load_exclusive(n));
|
||||
match(Set newval (GetAndAddI mem incr));
|
||||
ins_cost(VOLATILE_REF_COST + 1);
|
||||
format %{ "get_and_addI_acq $newval, [$mem], $incr" %}
|
||||
ins_encode %{
|
||||
__ atomic_addalw($newval$$Register, $incr$$constant, as_Register($mem$$base));
|
||||
%}
|
||||
ins_pipe(pipe_serial);
|
||||
%}
|
||||
|
||||
instruct get_and_addIi_no_resAcq(indirect mem, Universe dummy, immIAddSub incr) %{
|
||||
predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_exclusive(n));
|
||||
match(Set dummy (GetAndAddI mem incr));
|
||||
ins_cost(VOLATILE_REF_COST);
|
||||
format %{ "get_and_addI_acq [$mem], $incr" %}
|
||||
ins_encode %{
|
||||
__ atomic_addalw(noreg, $incr$$constant, as_Register($mem$$base));
|
||||
%}
|
||||
ins_pipe(pipe_serial);
|
||||
%}
|
||||
|
||||
// Manifest a CmpL result in an integer register.
|
||||
// (src1 < src2) ? -1 : ((src1 > src2) ? 1 : 0)
|
||||
instruct cmpL3_reg_reg(iRegINoSp dst, iRegL src1, iRegL src2, rFlagsReg flags)
|
||||
|
||||
@ -179,10 +179,10 @@ void CompiledDirectStaticCall::set_to_interpreted(const methodHandle& callee, ad
|
||||
}
|
||||
|
||||
void CompiledDirectStaticCall::set_stub_to_clean(static_stub_Relocation* static_stub) {
|
||||
assert (CompiledIC_lock->is_locked() || SafepointSynchronize::is_at_safepoint(), "mt unsafe call");
|
||||
// Reset stub.
|
||||
address stub = static_stub->addr();
|
||||
assert(stub != NULL, "stub not found");
|
||||
assert(CompiledICLocker::is_safe(stub), "mt unsafe call");
|
||||
// Creation also verifies the object.
|
||||
NativeMovConstReg* method_holder = nativeMovConstReg_at(stub);
|
||||
method_holder->set_data(0);
|
||||
|
||||
@ -69,10 +69,10 @@ void CompiledPltStaticCall::set_to_interpreted(const methodHandle& callee, addre
|
||||
|
||||
#ifdef NEVER_CALLED
|
||||
void CompiledPltStaticCall::set_stub_to_clean(static_stub_Relocation* static_stub) {
|
||||
assert (CompiledIC_lock->is_locked() || SafepointSynchronize::is_at_safepoint(), "mt unsafe call");
|
||||
// Reset stub.
|
||||
address stub = static_stub->addr();
|
||||
assert(stub != NULL, "stub not found");
|
||||
assert(CompiledICLocker::is_safe(stub), "mt unsafe call");
|
||||
// Creation also verifies the object.
|
||||
NativeLoadGot* method_loader = nativeLoadGot_at(stub);
|
||||
NativeGotJump* jump = nativeGotJump_at(method_loader->next_instruction_address());
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2000, 2017, Oracle and/or its affiliates. All rights reserved.
|
||||
* Copyright (c) 2000, 2018, Oracle and/or its affiliates. All rights reserved.
|
||||
* Copyright (c) 2015, Red Hat Inc. All rights reserved.
|
||||
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
|
||||
*
|
||||
@ -65,8 +65,6 @@ define_pd_global(intx, StackReservedPages, DEFAULT_STACK_RESERVED_PAGES);
|
||||
define_pd_global(bool, RewriteBytecodes, true);
|
||||
define_pd_global(bool, RewriteFrequentPairs, true);
|
||||
|
||||
define_pd_global(bool, UseMembar, true);
|
||||
|
||||
define_pd_global(bool, PreserveFramePointer, false);
|
||||
|
||||
// GC Ergo Flags
|
||||
|
||||
@ -288,10 +288,6 @@ address MacroAssembler::target_addr_for_insn(address insn_addr, unsigned insn) {
|
||||
return address(((uint64_t)insn_addr + (offset << 2)));
|
||||
}
|
||||
|
||||
void MacroAssembler::serialize_memory(Register thread, Register tmp) {
|
||||
dsb(Assembler::SY);
|
||||
}
|
||||
|
||||
void MacroAssembler::safepoint_poll(Label& slow_path) {
|
||||
if (SafepointMechanism::uses_thread_local_poll()) {
|
||||
ldr(rscratch1, Address(rthread, Thread::polling_page_offset()));
|
||||
@ -2367,21 +2363,18 @@ void MacroAssembler::cmpxchg(Register addr, Register expected,
|
||||
bool weak,
|
||||
Register result) {
|
||||
if (result == noreg) result = rscratch1;
|
||||
BLOCK_COMMENT("cmpxchg {");
|
||||
if (UseLSE) {
|
||||
mov(result, expected);
|
||||
lse_cas(result, new_val, addr, size, acquire, release, /*not_pair*/ true);
|
||||
cmp(result, expected);
|
||||
compare_eq(result, expected, size);
|
||||
} else {
|
||||
BLOCK_COMMENT("cmpxchg {");
|
||||
Label retry_load, done;
|
||||
if ((VM_Version::features() & VM_Version::CPU_STXR_PREFETCH))
|
||||
prfm(Address(addr), PSTL1STRM);
|
||||
bind(retry_load);
|
||||
load_exclusive(result, addr, size, acquire);
|
||||
if (size == xword)
|
||||
cmp(result, expected);
|
||||
else
|
||||
cmpw(result, expected);
|
||||
compare_eq(result, expected, size);
|
||||
br(Assembler::NE, done);
|
||||
store_exclusive(rscratch1, new_val, addr, size, release);
|
||||
if (weak) {
|
||||
@ -2390,10 +2383,28 @@ void MacroAssembler::cmpxchg(Register addr, Register expected,
|
||||
cbnzw(rscratch1, retry_load);
|
||||
}
|
||||
bind(done);
|
||||
BLOCK_COMMENT("} cmpxchg");
|
||||
}
|
||||
BLOCK_COMMENT("} cmpxchg");
|
||||
}
|
||||
|
||||
// A generic comparison. Only compares for equality, clobbers rscratch1.
|
||||
void MacroAssembler::compare_eq(Register rm, Register rn, enum operand_size size) {
|
||||
if (size == xword) {
|
||||
cmp(rm, rn);
|
||||
} else if (size == word) {
|
||||
cmpw(rm, rn);
|
||||
} else if (size == halfword) {
|
||||
eorw(rscratch1, rm, rn);
|
||||
ands(zr, rscratch1, 0xffff);
|
||||
} else if (size == byte) {
|
||||
eorw(rscratch1, rm, rn);
|
||||
ands(zr, rscratch1, 0xff);
|
||||
} else {
|
||||
ShouldNotReachHere();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static bool different(Register a, RegisterOrConstant b, Register c) {
|
||||
if (b.is_constant())
|
||||
return a != c;
|
||||
|
||||
@ -582,6 +582,7 @@ public:
|
||||
|
||||
virtual void null_check(Register reg, int offset = -1);
|
||||
static bool needs_explicit_null_check(intptr_t offset);
|
||||
static bool uses_implicit_null_check(void* address);
|
||||
|
||||
static address target_addr_for_insn(address insn_addr, unsigned insn);
|
||||
static address target_addr_for_insn(address insn_addr) {
|
||||
@ -975,9 +976,6 @@ public:
|
||||
Register tmp,
|
||||
int offset);
|
||||
|
||||
// Support for serializing memory accesses between threads
|
||||
void serialize_memory(Register thread, Register tmp);
|
||||
|
||||
// Arithmetics
|
||||
|
||||
void addptr(const Address &dst, int32_t src);
|
||||
@ -1020,7 +1018,10 @@ public:
|
||||
enum operand_size size,
|
||||
bool acquire, bool release, bool weak,
|
||||
Register result);
|
||||
private:
|
||||
void compare_eq(Register rn, Register rm, enum operand_size size);
|
||||
|
||||
public:
|
||||
// Calls
|
||||
|
||||
address trampoline_call(Address entry, CodeBuffer *cbuf = NULL);
|
||||
|
||||
@ -25,6 +25,7 @@
|
||||
|
||||
#include "precompiled.hpp"
|
||||
#include "asm/macroAssembler.hpp"
|
||||
#include "code/compiledIC.hpp"
|
||||
#include "memory/resourceArea.hpp"
|
||||
#include "nativeInst_aarch64.hpp"
|
||||
#include "oops/oop.inline.hpp"
|
||||
@ -178,7 +179,8 @@ address NativeCall::destination() const {
|
||||
// during code generation, where no patching lock is needed.
|
||||
void NativeCall::set_destination_mt_safe(address dest, bool assert_lock) {
|
||||
assert(!assert_lock ||
|
||||
(Patching_lock->is_locked() || SafepointSynchronize::is_at_safepoint()),
|
||||
(Patching_lock->is_locked() || SafepointSynchronize::is_at_safepoint()) ||
|
||||
CompiledICLocker::is_safe(addr_at(0)),
|
||||
"concurrent code patching");
|
||||
|
||||
ResourceMark rm;
|
||||
|
||||
@ -1950,21 +1950,10 @@ nmethod* SharedRuntime::generate_native_wrapper(MacroAssembler* masm,
|
||||
// didn't see any synchronization is progress, and escapes.
|
||||
__ mov(rscratch1, _thread_in_native_trans);
|
||||
|
||||
if (UseMembar) {
|
||||
__ strw(rscratch1, Address(rthread, JavaThread::thread_state_offset()));
|
||||
__ strw(rscratch1, Address(rthread, JavaThread::thread_state_offset()));
|
||||
|
||||
// Force this write out before the read below
|
||||
__ dmb(Assembler::ISH);
|
||||
} else {
|
||||
__ lea(rscratch2, Address(rthread, JavaThread::thread_state_offset()));
|
||||
__ stlrw(rscratch1, rscratch2);
|
||||
|
||||
// Write serialization page so VM thread can do a pseudo remote membar.
|
||||
// We use the current thread pointer to calculate a thread specific
|
||||
// offset to write to within the page. This minimizes bus traffic
|
||||
// due to cache line collision.
|
||||
__ serialize_memory(rthread, r2);
|
||||
}
|
||||
// Force this write out before the read below
|
||||
__ dmb(Assembler::ISH);
|
||||
|
||||
// check for safepoint operation in progress and/or pending suspend requests
|
||||
Label safepoint_in_progress, safepoint_in_progress_done;
|
||||
|
||||
@ -1394,16 +1394,8 @@ address TemplateInterpreterGenerator::generate_native_entry(bool synchronized) {
|
||||
__ lea(rscratch2, Address(rthread, JavaThread::thread_state_offset()));
|
||||
__ stlrw(rscratch1, rscratch2);
|
||||
|
||||
if (UseMembar) {
|
||||
// Force this write out before the read below
|
||||
__ dmb(Assembler::ISH);
|
||||
} else {
|
||||
// Write serialization page so VM thread can do a pseudo remote membar.
|
||||
// We use the current thread pointer to calculate a thread specific
|
||||
// offset to write to within the page. This minimizes bus traffic
|
||||
// due to cache line collision.
|
||||
__ serialize_memory(rthread, rscratch2);
|
||||
}
|
||||
// Force this write out before the read below
|
||||
__ dmb(Assembler::ISH);
|
||||
|
||||
// check for safepoint operation in progress and/or pending suspend requests
|
||||
{
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
|
||||
* Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
|
||||
* Copyright (c) 2015, Red Hat Inc. All rights reserved.
|
||||
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
|
||||
*
|
||||
@ -217,11 +217,6 @@ void VM_Version::get_processor_features() {
|
||||
if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
|
||||
FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
|
||||
}
|
||||
#ifdef COMPILER2
|
||||
if (FLAG_IS_DEFAULT(UseFPUForSpilling)) {
|
||||
FLAG_SET_DEFAULT(UseFPUForSpilling, true);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
// Cortex A53
|
||||
|
||||
@ -137,10 +137,10 @@ void CompiledDirectStaticCall::set_to_interpreted(const methodHandle& callee, ad
|
||||
}
|
||||
|
||||
void CompiledDirectStaticCall::set_stub_to_clean(static_stub_Relocation* static_stub) {
|
||||
assert (CompiledIC_lock->is_locked() || SafepointSynchronize::is_at_safepoint(), "mt unsafe call");
|
||||
// Reset stub.
|
||||
address stub = static_stub->addr();
|
||||
assert(stub != NULL, "stub not found");
|
||||
assert(CompiledICLocker::is_safe(stub), "mt unsafe call");
|
||||
// Creation also verifies the object.
|
||||
NativeMovConstReg* method_holder = nativeMovConstReg_at(stub);
|
||||
NativeJump* jump = nativeJump_at(method_holder->next_instruction_address());
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2008, 2017, Oracle and/or its affiliates. All rights reserved.
|
||||
* Copyright (c) 2008, 2018, Oracle and/or its affiliates. All rights reserved.
|
||||
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
|
||||
*
|
||||
* This code is free software; you can redistribute it and/or modify it
|
||||
@ -65,8 +65,6 @@ define_pd_global(intx, InlineSmallCode, 1500);
|
||||
define_pd_global(bool, RewriteBytecodes, true);
|
||||
define_pd_global(bool, RewriteFrequentPairs, true);
|
||||
|
||||
define_pd_global(bool, UseMembar, true);
|
||||
|
||||
define_pd_global(bool, PreserveFramePointer, false);
|
||||
|
||||
// GC Ergo Flags
|
||||
|
||||
@ -358,6 +358,7 @@ public:
|
||||
void zero_memory(Register start, Register end, Register tmp);
|
||||
|
||||
static bool needs_explicit_null_check(intptr_t offset);
|
||||
static bool uses_implicit_null_check(void* address);
|
||||
|
||||
void arm_stack_overflow_check(int frame_size_in_bytes, Register tmp);
|
||||
void arm_stack_overflow_check(Register Rsize, Register tmp);
|
||||
@ -1095,4 +1096,3 @@ private:
|
||||
|
||||
|
||||
#endif // CPU_ARM_VM_MACROASSEMBLER_ARM_HPP
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
|
||||
* Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
|
||||
* Copyright (c) 2012, 2015 SAP SE. All rights reserved.
|
||||
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
|
||||
*
|
||||
@ -197,10 +197,10 @@ void CompiledDirectStaticCall::set_to_interpreted(const methodHandle& callee, ad
|
||||
}
|
||||
|
||||
void CompiledDirectStaticCall::set_stub_to_clean(static_stub_Relocation* static_stub) {
|
||||
assert (CompiledIC_lock->is_locked() || SafepointSynchronize::is_at_safepoint(), "mt unsafe call");
|
||||
// Reset stub.
|
||||
address stub = static_stub->addr();
|
||||
assert(stub != NULL, "stub not found");
|
||||
assert(CompiledICLocker::is_safe(stub), "mt unsafe call");
|
||||
// Creation also verifies the object.
|
||||
NativeMovConstReg* method_holder = nativeMovConstReg_at(stub + IC_pos_in_java_to_interp_stub);
|
||||
NativeJump* jump = nativeJump_at(method_holder->next_instruction_address());
|
||||
|
||||
@ -69,8 +69,6 @@ define_pd_global(intx, InlineSmallCode, 1500);
|
||||
define_pd_global(bool, RewriteBytecodes, true);
|
||||
define_pd_global(bool, RewriteFrequentPairs, true);
|
||||
|
||||
define_pd_global(bool, UseMembar, true);
|
||||
|
||||
define_pd_global(bool, PreserveFramePointer, false);
|
||||
|
||||
// GC Ergo Flags
|
||||
|
||||
@ -1302,35 +1302,6 @@ bool MacroAssembler::is_load_from_polling_page(int instruction, void* ucontext,
|
||||
#endif
|
||||
}
|
||||
|
||||
bool MacroAssembler::is_memory_serialization(int instruction, JavaThread* thread, void* ucontext) {
|
||||
#ifdef LINUX
|
||||
ucontext_t* uc = (ucontext_t*) ucontext;
|
||||
|
||||
if (is_stwx(instruction) || is_stwux(instruction)) {
|
||||
int ra = inv_ra_field(instruction);
|
||||
int rb = inv_rb_field(instruction);
|
||||
|
||||
// look up content of ra and rb in ucontext
|
||||
address ra_val=(address)uc->uc_mcontext.regs->gpr[ra];
|
||||
long rb_val=(long)uc->uc_mcontext.regs->gpr[rb];
|
||||
return os::is_memory_serialize_page(thread, ra_val+rb_val);
|
||||
} else if (is_stw(instruction) || is_stwu(instruction)) {
|
||||
int ra = inv_ra_field(instruction);
|
||||
int d1 = inv_d1_field(instruction);
|
||||
|
||||
// look up content of ra in ucontext
|
||||
address ra_val=(address)uc->uc_mcontext.regs->gpr[ra];
|
||||
return os::is_memory_serialize_page(thread, ra_val+d1);
|
||||
} else {
|
||||
return false;
|
||||
}
|
||||
#else
|
||||
// workaround not needed on !LINUX :-)
|
||||
ShouldNotCallThis();
|
||||
return false;
|
||||
#endif
|
||||
}
|
||||
|
||||
void MacroAssembler::bang_stack_with_offset(int offset) {
|
||||
// When increasing the stack, the old stack pointer will be written
|
||||
// to the new top of stack according to the PPC64 abi.
|
||||
@ -3046,27 +3017,6 @@ void MacroAssembler::compiler_fast_unlock_object(ConditionRegister flag, Registe
|
||||
// flag == NE indicates failure
|
||||
}
|
||||
|
||||
// Write serialization page so VM thread can do a pseudo remote membar.
|
||||
// We use the current thread pointer to calculate a thread specific
|
||||
// offset to write to within the page. This minimizes bus traffic
|
||||
// due to cache line collision.
|
||||
void MacroAssembler::serialize_memory(Register thread, Register tmp1, Register tmp2) {
|
||||
srdi(tmp2, thread, os::get_serialize_page_shift_count());
|
||||
|
||||
int mask = os::vm_page_size() - sizeof(int);
|
||||
if (Assembler::is_simm(mask, 16)) {
|
||||
andi(tmp2, tmp2, mask);
|
||||
} else {
|
||||
lis(tmp1, (int)((signed short) (mask >> 16)));
|
||||
ori(tmp1, tmp1, mask & 0x0000ffff);
|
||||
andr(tmp2, tmp2, tmp1);
|
||||
}
|
||||
|
||||
load_const(tmp1, (long) os::get_memory_serialize_page());
|
||||
release();
|
||||
stwx(R0, tmp1, tmp2);
|
||||
}
|
||||
|
||||
void MacroAssembler::safepoint_poll(Label& slow_path, Register temp_reg) {
|
||||
if (SafepointMechanism::uses_thread_local_poll()) {
|
||||
ld(temp_reg, in_bytes(Thread::polling_page_offset()), R16_thread);
|
||||
|
||||
@ -395,11 +395,6 @@ class MacroAssembler: public Assembler {
|
||||
static bool is_load_from_polling_page(int instruction, void* ucontext/*may be NULL*/,
|
||||
address* polling_address_ptr = NULL);
|
||||
|
||||
// Check whether instruction is a write access to the memory
|
||||
// serialization page realized by one of the instructions stw, stwu,
|
||||
// stwx, or stwux.
|
||||
static bool is_memory_serialization(int instruction, JavaThread* thread, void* ucontext);
|
||||
|
||||
// Support for NULL-checks
|
||||
//
|
||||
// Generates code that causes a NULL OS exception if the content of reg is NULL.
|
||||
@ -645,9 +640,6 @@ class MacroAssembler: public Assembler {
|
||||
Register tmp1, Register tmp2, Register tmp3,
|
||||
bool try_bias = UseBiasedLocking, bool use_rtm = false);
|
||||
|
||||
// Support for serializing memory accesses between threads
|
||||
void serialize_memory(Register thread, Register tmp1, Register tmp2);
|
||||
|
||||
// Check if safepoint requested and if so branch
|
||||
void safepoint_poll(Label& slow_path, Register temp_reg);
|
||||
|
||||
@ -667,6 +659,7 @@ class MacroAssembler: public Assembler {
|
||||
void get_vm_result_2(Register metadata_result);
|
||||
|
||||
static bool needs_explicit_null_check(intptr_t offset);
|
||||
static bool uses_implicit_null_check(void* address);
|
||||
|
||||
// Trap-instruction-based checks.
|
||||
// Range checks can be distinguished from zero checks as they check 32 bit,
|
||||
|
||||
@ -25,6 +25,7 @@
|
||||
|
||||
#include "precompiled.hpp"
|
||||
#include "asm/macroAssembler.inline.hpp"
|
||||
#include "code/compiledIC.hpp"
|
||||
#include "memory/resourceArea.hpp"
|
||||
#include "nativeInst_ppc.hpp"
|
||||
#include "oops/compressedOops.inline.hpp"
|
||||
@ -94,7 +95,8 @@ address NativeCall::destination() const {
|
||||
// during code generation, where no patching lock is needed.
|
||||
void NativeCall::set_destination_mt_safe(address dest, bool assert_lock) {
|
||||
assert(!assert_lock ||
|
||||
(Patching_lock->is_locked() || SafepointSynchronize::is_at_safepoint()),
|
||||
(Patching_lock->is_locked() || SafepointSynchronize::is_at_safepoint()) ||
|
||||
CompiledICLocker::is_safe(addr_at(0)),
|
||||
"concurrent code patching");
|
||||
|
||||
ResourceMark rm;
|
||||
|
||||
@ -100,12 +100,6 @@ class NativeInstruction {
|
||||
return MacroAssembler::is_load_from_polling_page(long_at(0), NULL);
|
||||
}
|
||||
|
||||
bool is_memory_serialization(JavaThread *thread, void *ucontext) {
|
||||
// Is the current instruction a write access of thread to the
|
||||
// memory serialization page?
|
||||
return MacroAssembler::is_memory_serialization(long_at(0), thread, ucontext);
|
||||
}
|
||||
|
||||
address get_stack_bang_address(void *ucontext) {
|
||||
// If long_at(0) is not a stack bang, return 0. Otherwise, return
|
||||
// banged address.
|
||||
|
||||
@ -7629,7 +7629,7 @@ instruct cmovI_reg(cmpOp cmp, flagsRegSrc crx, iRegIdst dst, iRegIsrc src) %{
|
||||
|
||||
format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
|
||||
// Worst case is branch + move + stop, no stop without scheduler
|
||||
size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
|
||||
size((false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8));
|
||||
ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
|
||||
ins_pipe(pipe_class_default);
|
||||
%}
|
||||
@ -7642,7 +7642,7 @@ instruct cmovI_imm(cmpOp cmp, flagsRegSrc crx, iRegIdst dst, immI16 src) %{
|
||||
|
||||
format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
|
||||
// Worst case is branch + move + stop, no stop without scheduler
|
||||
size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
|
||||
size((false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8));
|
||||
ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
|
||||
ins_pipe(pipe_class_default);
|
||||
%}
|
||||
@ -7675,7 +7675,7 @@ instruct cmovL_reg(cmpOp cmp, flagsRegSrc crx, iRegLdst dst, iRegLsrc src) %{
|
||||
|
||||
format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
|
||||
// Worst case is branch + move + stop, no stop without scheduler.
|
||||
size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
|
||||
size((false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8));
|
||||
ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
|
||||
ins_pipe(pipe_class_default);
|
||||
%}
|
||||
@ -7688,7 +7688,7 @@ instruct cmovL_imm(cmpOp cmp, flagsRegSrc crx, iRegLdst dst, immL16 src) %{
|
||||
|
||||
format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
|
||||
// Worst case is branch + move + stop, no stop without scheduler.
|
||||
size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
|
||||
size((false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8));
|
||||
ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
|
||||
ins_pipe(pipe_class_default);
|
||||
%}
|
||||
@ -7722,7 +7722,7 @@ instruct cmovN_reg(cmpOp cmp, flagsRegSrc crx, iRegNdst dst, iRegNsrc src) %{
|
||||
|
||||
format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
|
||||
// Worst case is branch + move + stop, no stop without scheduler.
|
||||
size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
|
||||
size((false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8));
|
||||
ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
|
||||
ins_pipe(pipe_class_default);
|
||||
%}
|
||||
@ -7735,7 +7735,7 @@ instruct cmovN_imm(cmpOp cmp, flagsRegSrc crx, iRegNdst dst, immN_0 src) %{
|
||||
|
||||
format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
|
||||
// Worst case is branch + move + stop, no stop without scheduler.
|
||||
size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
|
||||
size((false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8));
|
||||
ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
|
||||
ins_pipe(pipe_class_default);
|
||||
%}
|
||||
@ -7768,7 +7768,7 @@ instruct cmovP_reg(cmpOp cmp, flagsRegSrc crx, iRegPdst dst, iRegP_N2P src) %{
|
||||
|
||||
format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
|
||||
// Worst case is branch + move + stop, no stop without scheduler.
|
||||
size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
|
||||
size((false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8));
|
||||
ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
|
||||
ins_pipe(pipe_class_default);
|
||||
%}
|
||||
@ -7781,7 +7781,7 @@ instruct cmovP_imm(cmpOp cmp, flagsRegSrc crx, iRegPdst dst, immP_0 src) %{
|
||||
|
||||
format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
|
||||
// Worst case is branch + move + stop, no stop without scheduler.
|
||||
size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
|
||||
size((false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8));
|
||||
ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
|
||||
ins_pipe(pipe_class_default);
|
||||
%}
|
||||
@ -7794,7 +7794,7 @@ instruct cmovF_reg(cmpOp cmp, flagsRegSrc crx, regF dst, regF src) %{
|
||||
|
||||
format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %}
|
||||
// Worst case is branch + move + stop, no stop without scheduler.
|
||||
size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
|
||||
size((false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8));
|
||||
ins_encode %{
|
||||
// TODO: PPC port $archOpcode(ppc64Opcode_cmovef);
|
||||
Label done;
|
||||
@ -7816,7 +7816,7 @@ instruct cmovD_reg(cmpOp cmp, flagsRegSrc crx, regD dst, regD src) %{
|
||||
|
||||
format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %}
|
||||
// Worst case is branch + move + stop, no stop without scheduler.
|
||||
size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
|
||||
size((false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8));
|
||||
ins_encode %{
|
||||
// TODO: PPC port $archOpcode(ppc64Opcode_cmovef);
|
||||
Label done;
|
||||
@ -9277,7 +9277,7 @@ instruct cmovI_bne_negI_reg(iRegIdst dst, flagsRegSrc crx, iRegIsrc src1) %{
|
||||
|
||||
format %{ "CMOVE $dst, neg($src1), $crx" %}
|
||||
// Worst case is branch + move + stop, no stop without scheduler.
|
||||
size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
|
||||
size((false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8));
|
||||
ins_encode %{
|
||||
// TODO: PPC port $archOpcode(ppc64Opcode_cmove);
|
||||
Label done;
|
||||
@ -9340,7 +9340,7 @@ instruct cmovL_bne_negL_reg(iRegLdst dst, flagsRegSrc crx, iRegLsrc src1) %{
|
||||
|
||||
format %{ "CMOVE $dst, neg($src1), $crx" %}
|
||||
// Worst case is branch + move + stop, no stop without scheduler.
|
||||
size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
|
||||
size((false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8));
|
||||
ins_encode %{
|
||||
// TODO: PPC port $archOpcode(ppc64Opcode_cmove);
|
||||
Label done;
|
||||
@ -11114,7 +11114,7 @@ instruct cmovI_bso_stackSlotL(iRegIdst dst, flagsRegSrc crx, stackSlotL src) %{
|
||||
|
||||
format %{ "cmovI $crx, $dst, $src" %}
|
||||
// Worst case is branch + move + stop, no stop without scheduler.
|
||||
size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
|
||||
size((false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8));
|
||||
ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
|
||||
ins_pipe(pipe_class_default);
|
||||
%}
|
||||
@ -11128,7 +11128,7 @@ instruct cmovI_bso_reg(iRegIdst dst, flagsRegSrc crx, regD src) %{
|
||||
|
||||
format %{ "cmovI $crx, $dst, $src" %}
|
||||
// Worst case is branch + move + stop, no stop without scheduler.
|
||||
size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
|
||||
size((false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8));
|
||||
ins_encode( enc_cmove_bso_reg(dst, crx, src) );
|
||||
ins_pipe(pipe_class_default);
|
||||
%}
|
||||
@ -11383,7 +11383,7 @@ instruct cmovL_bso_stackSlotL(iRegLdst dst, flagsRegSrc crx, stackSlotL src) %{
|
||||
|
||||
format %{ "cmovL $crx, $dst, $src" %}
|
||||
// Worst case is branch + move + stop, no stop without scheduler.
|
||||
size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
|
||||
size((false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8));
|
||||
ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
|
||||
ins_pipe(pipe_class_default);
|
||||
%}
|
||||
@ -11397,7 +11397,7 @@ instruct cmovL_bso_reg(iRegLdst dst, flagsRegSrc crx, regD src) %{
|
||||
|
||||
format %{ "cmovL $crx, $dst, $src" %}
|
||||
// Worst case is branch + move + stop, no stop without scheduler.
|
||||
size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
|
||||
size((false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8));
|
||||
ins_encode( enc_cmove_bso_reg(dst, crx, src) );
|
||||
ins_pipe(pipe_class_default);
|
||||
%}
|
||||
@ -11890,7 +11890,7 @@ instruct cmovI_conIvalueMinus1_conIvalue1(iRegIdst dst, flagsRegSrc crx) %{
|
||||
|
||||
format %{ "cmovI $crx, $dst, -1, 0, +1" %}
|
||||
// Worst case is branch + move + branch + move + stop, no stop without scheduler.
|
||||
size(false /* TODO: PPC PORTInsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 20 : 16);
|
||||
size((false /* TODO: PPC PORTInsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 20 : 16));
|
||||
ins_encode %{
|
||||
// TODO: PPC port $archOpcode(ppc64Opcode_cmove);
|
||||
Label done;
|
||||
@ -12229,7 +12229,7 @@ instruct cmov_bns_less(flagsReg crx) %{
|
||||
|
||||
format %{ "cmov $crx" %}
|
||||
// Worst case is branch + move + stop, no stop without scheduler.
|
||||
size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 16 : 12);
|
||||
size((false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 16 : 12));
|
||||
ins_encode %{
|
||||
// TODO: PPC port $archOpcode(ppc64Opcode_cmovecr);
|
||||
Label done;
|
||||
|
||||
@ -2430,16 +2430,8 @@ nmethod *SharedRuntime::generate_native_wrapper(MacroAssembler *masm,
|
||||
{
|
||||
Label no_block, sync;
|
||||
|
||||
if (UseMembar) {
|
||||
// Force this write out before the read below.
|
||||
__ fence();
|
||||
} else {
|
||||
// Write serialization page so VM thread can do a pseudo remote membar.
|
||||
// We use the current thread pointer to calculate a thread specific
|
||||
// offset to write to within the page. This minimizes bus traffic
|
||||
// due to cache line collision.
|
||||
__ serialize_memory(R16_thread, r_temp_4, r_temp_5);
|
||||
}
|
||||
// Force this write out before the read below.
|
||||
__ fence();
|
||||
|
||||
Register sync_state_addr = r_temp_4;
|
||||
Register sync_state = r_temp_5;
|
||||
|
||||
@ -1486,16 +1486,7 @@ address TemplateInterpreterGenerator::generate_native_entry(bool synchronized) {
|
||||
__ li(R0/*thread_state*/, _thread_in_native_trans);
|
||||
__ release();
|
||||
__ stw(R0/*thread_state*/, thread_(thread_state));
|
||||
if (UseMembar) {
|
||||
__ fence();
|
||||
}
|
||||
// Write serialization page so that the VM thread can do a pseudo remote
|
||||
// membar. We use the current thread pointer to calculate a thread
|
||||
// specific offset to write to within the page. This minimizes bus
|
||||
// traffic due to cache line collision.
|
||||
else {
|
||||
__ serialize_memory(R16_thread, R11_scratch1, R12_scratch2);
|
||||
}
|
||||
__ fence();
|
||||
|
||||
// Now before we return to java we must look for a current safepoint
|
||||
// (a new safepoint can not start since we entered native_trans).
|
||||
|
||||
@ -127,10 +127,10 @@ void CompiledDirectStaticCall::set_to_interpreted(const methodHandle& callee, ad
|
||||
}
|
||||
|
||||
void CompiledDirectStaticCall::set_stub_to_clean(static_stub_Relocation* static_stub) {
|
||||
assert (CompiledIC_lock->is_locked() || SafepointSynchronize::is_at_safepoint(), "mt unsafe call");
|
||||
// Reset stub.
|
||||
address stub = static_stub->addr();
|
||||
assert(stub != NULL, "stub not found");
|
||||
assert(CompiledICLocker::is_safe(stub), "mt unsafe call");
|
||||
// Creation also verifies the object.
|
||||
NativeMovConstReg* method_holder = nativeMovConstReg_at(stub + NativeCall::get_IC_pos_in_java_to_interp_stub());
|
||||
NativeJump* jump = nativeJump_at(method_holder->next_instruction_address());
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2016, 2017 Oracle and/or its affiliates. All rights reserved.
|
||||
* Copyright (c) 2016, 2018, Oracle and/or its affiliates. All rights reserved.
|
||||
* Copyright (c) 2016, 2018 SAP SE. All rights reserved.
|
||||
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
|
||||
*
|
||||
@ -71,8 +71,6 @@ define_pd_global(intx, StackReservedPages, DEFAULT_STACK_RESERVED_PAGE
|
||||
define_pd_global(bool, RewriteBytecodes, true);
|
||||
define_pd_global(bool, RewriteFrequentPairs, true);
|
||||
|
||||
define_pd_global(bool, UseMembar, true);
|
||||
|
||||
define_pd_global(bool, PreserveFramePointer, false);
|
||||
|
||||
// GC Ergo Flags
|
||||
|
||||
@ -2685,33 +2685,6 @@ uint MacroAssembler::get_poll_register(address instr_loc) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
bool MacroAssembler::is_memory_serialization(int instruction, JavaThread* thread, void* ucontext) {
|
||||
ShouldNotCallThis();
|
||||
return false;
|
||||
}
|
||||
|
||||
// Write serialization page so VM thread can do a pseudo remote membar
|
||||
// We use the current thread pointer to calculate a thread specific
|
||||
// offset to write to within the page. This minimizes bus traffic
|
||||
// due to cache line collision.
|
||||
void MacroAssembler::serialize_memory(Register thread, Register tmp1, Register tmp2) {
|
||||
assert_different_registers(tmp1, tmp2);
|
||||
z_sllg(tmp2, thread, os::get_serialize_page_shift_count());
|
||||
load_const_optimized(tmp1, (long) os::get_memory_serialize_page());
|
||||
|
||||
int mask = os::get_serialize_page_mask();
|
||||
if (Immediate::is_uimm16(mask)) {
|
||||
z_nill(tmp2, mask);
|
||||
z_llghr(tmp2, tmp2);
|
||||
} else {
|
||||
z_nilf(tmp2, mask);
|
||||
z_llgfr(tmp2, tmp2);
|
||||
}
|
||||
|
||||
z_release();
|
||||
z_st(Z_R0, 0, tmp2, tmp1);
|
||||
}
|
||||
|
||||
void MacroAssembler::safepoint_poll(Label& slow_path, Register temp_reg) {
|
||||
if (SafepointMechanism::uses_thread_local_poll()) {
|
||||
const Address poll_byte_addr(Z_thread, in_bytes(Thread::polling_page_offset()) + 7 /* Big Endian */);
|
||||
|
||||
@ -635,13 +635,6 @@ class MacroAssembler: public Assembler {
|
||||
// Extract poll register from instruction.
|
||||
static uint get_poll_register(address instr_loc);
|
||||
|
||||
// Check if instruction is a write access to the memory serialization page
|
||||
// realized by one of the instructions stw, stwu, stwx, or stwux.
|
||||
static bool is_memory_serialization(int instruction, JavaThread* thread, void* ucontext);
|
||||
|
||||
// Support for serializing memory accesses between threads.
|
||||
void serialize_memory(Register thread, Register tmp1, Register tmp2);
|
||||
|
||||
// Check if safepoint requested and if so branch
|
||||
void safepoint_poll(Label& slow_path, Register temp_reg);
|
||||
|
||||
@ -779,6 +772,7 @@ class MacroAssembler: public Assembler {
|
||||
|
||||
void null_check(Register reg, Register tmp = Z_R0, int64_t offset = -1);
|
||||
static bool needs_explicit_null_check(intptr_t offset); // Implemented in shared file ?!
|
||||
static bool uses_implicit_null_check(void* address);
|
||||
|
||||
// Klass oop manipulations if compressed.
|
||||
void encode_klass_not_null(Register dst, Register src = noreg);
|
||||
|
||||
@ -104,12 +104,6 @@ class NativeInstruction {
|
||||
return MacroAssembler::get_poll_register(addr_at(0));
|
||||
}
|
||||
|
||||
bool is_memory_serialization(JavaThread *thread, void *ucontext) {
|
||||
// Is the current instruction a write access of thread to the
|
||||
// memory serialization page?
|
||||
return MacroAssembler::is_memory_serialization(long_at(0), thread, ucontext);
|
||||
}
|
||||
|
||||
public:
|
||||
|
||||
// The output of __ breakpoint_trap().
|
||||
|
||||
@ -6480,7 +6480,7 @@ instruct divModI_reg_divmod(roddRegI dst1src1, revenRegI dst2, noOdd_iRegI src2,
|
||||
match(DivModI dst1src1 src2);
|
||||
effect(KILL cr);
|
||||
ins_cost(2 * DEFAULT_COST + BRANCH_COST);
|
||||
size(VM_Version::has_CompareBranch() ? 24 : 26);
|
||||
size((VM_Version::has_CompareBranch() ? 24 : 26));
|
||||
format %{ "DIVMODI ($dst1src1, $dst2) $src2" %}
|
||||
ins_encode %{
|
||||
Register d1s1 = $dst1src1$$Register;
|
||||
@ -6513,7 +6513,7 @@ instruct divI_reg_reg(roddRegI dst, iRegI src1, noOdd_iRegI src2, revenRegI tmp,
|
||||
match(Set dst (DivI src1 src2));
|
||||
effect(KILL tmp, KILL cr);
|
||||
ins_cost(2 * DEFAULT_COST + BRANCH_COST);
|
||||
size(VM_Version::has_CompareBranch() ? 20 : 22);
|
||||
size((VM_Version::has_CompareBranch() ? 20 : 22));
|
||||
format %{ "DIV_checked $dst, $src1,$src2\t # treats special case 0x80../-1" %}
|
||||
ins_encode %{
|
||||
Register a = $src1$$Register;
|
||||
@ -6564,7 +6564,7 @@ instruct divModL_reg_divmod(roddRegL dst1src1, revenRegL dst2, iRegL src2, flags
|
||||
match(DivModL dst1src1 src2);
|
||||
effect(KILL cr);
|
||||
ins_cost(2 * DEFAULT_COST + BRANCH_COST);
|
||||
size(VM_Version::has_CompareBranch() ? 22 : 24);
|
||||
size((VM_Version::has_CompareBranch() ? 22 : 24));
|
||||
format %{ "DIVMODL ($dst1src1, $dst2) $src2" %}
|
||||
ins_encode %{
|
||||
Register d1s1 = $dst1src1$$Register;
|
||||
@ -6594,7 +6594,7 @@ instruct divL_reg_reg(roddRegL dst, iRegL src, revenRegL tmp, flagsReg cr) %{
|
||||
match(Set dst (DivL dst src));
|
||||
effect(KILL tmp, KILL cr);
|
||||
ins_cost(2 * DEFAULT_COST + BRANCH_COST);
|
||||
size(VM_Version::has_CompareBranch() ? 18 : 20);
|
||||
size((VM_Version::has_CompareBranch() ? 18 : 20));
|
||||
format %{ "DIVG_checked $dst, $src\t # long, treats special case 0x80../-1" %}
|
||||
ins_encode %{
|
||||
Register b = $src$$Register;
|
||||
|
||||
@ -2161,16 +2161,8 @@ nmethod *SharedRuntime::generate_native_wrapper(MacroAssembler *masm,
|
||||
|
||||
save_native_result(masm, ret_type, workspace_slot_offset); // Make Z_R2 available as work reg.
|
||||
|
||||
if (UseMembar) {
|
||||
// Force this write out before the read below.
|
||||
__ z_fence();
|
||||
} else {
|
||||
// Write serialization page so VM thread can do a pseudo remote membar.
|
||||
// We use the current thread pointer to calculate a thread specific
|
||||
// offset to write to within the page. This minimizes bus traffic
|
||||
// due to cache line collision.
|
||||
__ serialize_memory(Z_thread, Z_R1, Z_R2);
|
||||
}
|
||||
// Force this write out before the read below.
|
||||
__ z_fence();
|
||||
|
||||
__ safepoint_poll(sync, Z_R1);
|
||||
|
||||
|
||||
@ -1598,15 +1598,8 @@ address TemplateInterpreterGenerator::generate_native_entry(bool synchronized) {
|
||||
// synchronization is progress, and escapes.
|
||||
|
||||
__ set_thread_state(_thread_in_native_trans);
|
||||
if (UseMembar) {
|
||||
__ z_fence();
|
||||
} else {
|
||||
// Write serialization page so VM thread can do a pseudo remote
|
||||
// membar. We use the current thread pointer to calculate a thread
|
||||
// specific offset to write to within the page. This minimizes bus
|
||||
// traffic due to cache line collision.
|
||||
__ serialize_memory(Z_thread, Z_R1, Z_R0);
|
||||
}
|
||||
__ z_fence();
|
||||
|
||||
// Now before we return to java we must look for a current safepoint
|
||||
// (a new safepoint can not start since we entered native_trans).
|
||||
// We must check here because a current safepoint could be modifying
|
||||
|
||||
@ -124,10 +124,10 @@ void CompiledDirectStaticCall::set_to_interpreted(const methodHandle& callee, ad
|
||||
}
|
||||
|
||||
void CompiledDirectStaticCall::set_stub_to_clean(static_stub_Relocation* static_stub) {
|
||||
assert (CompiledIC_lock->is_locked() || SafepointSynchronize::is_at_safepoint(), "mt unsafe call");
|
||||
// Reset stub.
|
||||
address stub = static_stub->addr();
|
||||
assert(stub != NULL, "stub not found");
|
||||
assert(CompiledICLocker::is_safe(stub), "mt unsafe call");
|
||||
// Creation also verifies the object.
|
||||
NativeMovConstReg* method_holder = nativeMovConstReg_at(stub);
|
||||
NativeJump* jump = nativeJump_at(method_holder->next_instruction_address());
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2000, 2017, Oracle and/or its affiliates. All rights reserved.
|
||||
* Copyright (c) 2000, 2018, Oracle and/or its affiliates. All rights reserved.
|
||||
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
|
||||
*
|
||||
* This code is free software; you can redistribute it and/or modify it
|
||||
@ -74,8 +74,6 @@ define_pd_global(intx, StackReservedPages, DEFAULT_STACK_RESERVED_PAGES);
|
||||
define_pd_global(bool, RewriteBytecodes, true);
|
||||
define_pd_global(bool, RewriteFrequentPairs, true);
|
||||
|
||||
define_pd_global(bool, UseMembar, true);
|
||||
|
||||
define_pd_global(bool, PreserveFramePointer, false);
|
||||
|
||||
// GC Ergo Flags
|
||||
|
||||
@ -236,24 +236,6 @@ void MacroAssembler::breakpoint_trap() {
|
||||
trap(ST_RESERVED_FOR_USER_0);
|
||||
}
|
||||
|
||||
// Write serialization page so VM thread can do a pseudo remote membar
|
||||
// We use the current thread pointer to calculate a thread specific
|
||||
// offset to write to within the page. This minimizes bus traffic
|
||||
// due to cache line collision.
|
||||
void MacroAssembler::serialize_memory(Register thread, Register tmp1, Register tmp2) {
|
||||
srl(thread, os::get_serialize_page_shift_count(), tmp2);
|
||||
if (Assembler::is_simm13(os::vm_page_size())) {
|
||||
and3(tmp2, (os::vm_page_size() - sizeof(int)), tmp2);
|
||||
}
|
||||
else {
|
||||
set((os::vm_page_size() - sizeof(int)), tmp1);
|
||||
and3(tmp2, tmp1, tmp2);
|
||||
}
|
||||
set(os::get_memory_serialize_page(), tmp1);
|
||||
st(G0, tmp1, tmp2);
|
||||
}
|
||||
|
||||
|
||||
void MacroAssembler::safepoint_poll(Label& slow_path, bool a, Register thread_reg, Register temp_reg) {
|
||||
if (SafepointMechanism::uses_thread_local_poll()) {
|
||||
ldx(Address(thread_reg, Thread::polling_page_offset()), temp_reg, 0);
|
||||
|
||||
@ -575,6 +575,7 @@ class MacroAssembler : public Assembler {
|
||||
|
||||
void null_check(Register reg, int offset = -1);
|
||||
static bool needs_explicit_null_check(intptr_t offset);
|
||||
static bool uses_implicit_null_check(void* address);
|
||||
|
||||
// support for delayed instructions
|
||||
MacroAssembler* delayed() { Assembler::delayed(); return this; }
|
||||
@ -951,9 +952,6 @@ public:
|
||||
void breakpoint_trap();
|
||||
void breakpoint_trap(Condition c, CC cc);
|
||||
|
||||
// Support for serializing memory accesses between threads
|
||||
void serialize_memory(Register thread, Register tmp1, Register tmp2);
|
||||
|
||||
void safepoint_poll(Label& slow_path, bool a, Register thread_reg, Register temp_reg);
|
||||
|
||||
// Stack frame creation/removal
|
||||
|
||||
@ -25,6 +25,7 @@
|
||||
#include "precompiled.hpp"
|
||||
#include "asm/macroAssembler.inline.hpp"
|
||||
#include "code/codeCache.hpp"
|
||||
#include "code/compiledIC.hpp"
|
||||
#include "memory/resourceArea.hpp"
|
||||
#include "nativeInst_sparc.hpp"
|
||||
#include "oops/oop.inline.hpp"
|
||||
@ -189,8 +190,9 @@ void NativeCall::replace_mt_safe(address instr_addr, address code_buffer) {
|
||||
//
|
||||
// Used in the runtime linkage of calls; see class CompiledIC.
|
||||
void NativeCall::set_destination_mt_safe(address dest) {
|
||||
assert(Patching_lock->is_locked() ||
|
||||
SafepointSynchronize::is_at_safepoint(), "concurrent code patching");
|
||||
assert((Patching_lock->is_locked() || SafepointSynchronize::is_at_safepoint()) ||
|
||||
CompiledICLocker::is_safe(addr_at(0)),
|
||||
"concurrent code patching");
|
||||
// set_destination uses set_long_at which does the ICache::invalidate
|
||||
set_destination(dest);
|
||||
}
|
||||
|
||||
@ -2372,16 +2372,8 @@ nmethod* SharedRuntime::generate_native_wrapper(MacroAssembler* masm,
|
||||
__ set(_thread_in_native_trans, G3_scratch);
|
||||
__ st(G3_scratch, G2_thread, JavaThread::thread_state_offset());
|
||||
|
||||
if (UseMembar) {
|
||||
// Force this write out before the read below
|
||||
__ membar(Assembler::StoreLoad);
|
||||
} else {
|
||||
// Write serialization page so VM thread can do a pseudo remote membar.
|
||||
// We use the current thread pointer to calculate a thread specific
|
||||
// offset to write to within the page. This minimizes bus traffic
|
||||
// due to cache line collision.
|
||||
__ serialize_memory(G2_thread, G1_scratch, G3_scratch);
|
||||
}
|
||||
// Force this write out before the read below
|
||||
__ membar(Assembler::StoreLoad);
|
||||
|
||||
Label L;
|
||||
Address suspend_state(G2_thread, JavaThread::suspend_flags_offset());
|
||||
|
||||
@ -1374,16 +1374,8 @@ address TemplateInterpreterGenerator::generate_native_entry(bool synchronized) {
|
||||
__ set(_thread_in_native_trans, G3_scratch);
|
||||
__ st(G3_scratch, thread_state);
|
||||
|
||||
if (UseMembar) {
|
||||
// Force this write out before the read below
|
||||
__ membar(Assembler::StoreLoad);
|
||||
} else {
|
||||
// Write serialization page so VM thread can do a pseudo remote membar.
|
||||
// We use the current thread pointer to calculate a thread specific
|
||||
// offset to write to within the page. This minimizes bus traffic
|
||||
// due to cache line collision.
|
||||
__ serialize_memory(G2_thread, G1_scratch, G3_scratch);
|
||||
}
|
||||
// Force this write out before the read below
|
||||
__ membar(Assembler::StoreLoad);
|
||||
|
||||
Label L;
|
||||
__ safepoint_poll(L, false, G2_thread, G3_scratch);
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2016, 2017, Oracle and/or its affiliates. All rights reserved.
|
||||
* Copyright (c) 2016, 2018, Oracle and/or its affiliates. All rights reserved.
|
||||
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
|
||||
*
|
||||
* This code is free software; you can redistribute it and/or modify it
|
||||
@ -88,10 +88,10 @@ void CompiledPltStaticCall::set_to_interpreted(const methodHandle& callee, addre
|
||||
|
||||
#ifdef NEVER_CALLED
|
||||
void CompiledPltStaticCall::set_stub_to_clean(static_stub_Relocation* static_stub) {
|
||||
assert (CompiledIC_lock->is_locked() || SafepointSynchronize::is_at_safepoint(), "mt unsafe call");
|
||||
// Reset stub.
|
||||
address stub = static_stub->addr();
|
||||
assert(stub != NULL, "stub not found");
|
||||
assert(CompiledICLocker::is_safe(stub), "mt unsafe call");
|
||||
// Creation also verifies the object.
|
||||
NativeLoadGot* method_loader = nativeLoadGot_at(stub);
|
||||
NativeGotJump* jump = nativeGotJump_at(method_loader->next_instruction_address());
|
||||
|
||||
@ -177,7 +177,7 @@ void CompiledDirectStaticCall::set_to_interpreted(const methodHandle& callee, ad
|
||||
}
|
||||
|
||||
void CompiledDirectStaticCall::set_stub_to_clean(static_stub_Relocation* static_stub) {
|
||||
assert (CompiledIC_lock->is_locked() || SafepointSynchronize::is_at_safepoint(), "mt unsafe call");
|
||||
assert(CompiledICLocker::is_safe(static_stub->addr()), "mt unsafe call");
|
||||
// Reset stub.
|
||||
address stub = static_stub->addr();
|
||||
assert(stub != NULL, "stub not found");
|
||||
|
||||
@ -84,8 +84,6 @@ define_pd_global(intx, StackReservedPages, DEFAULT_STACK_RESERVED_PAGES);
|
||||
define_pd_global(bool, RewriteBytecodes, true);
|
||||
define_pd_global(bool, RewriteFrequentPairs, true);
|
||||
|
||||
define_pd_global(bool, UseMembar, true);
|
||||
|
||||
// GC Ergo Flags
|
||||
define_pd_global(size_t, CMSYoungGenPerWorker, 64*M); // default max size of CMS young gen, per GC worker thread
|
||||
|
||||
|
||||
@ -3517,22 +3517,6 @@ void MacroAssembler::save_rax(Register tmp) {
|
||||
else if (tmp != rax) mov(tmp, rax);
|
||||
}
|
||||
|
||||
// Write serialization page so VM thread can do a pseudo remote membar.
|
||||
// We use the current thread pointer to calculate a thread specific
|
||||
// offset to write to within the page. This minimizes bus traffic
|
||||
// due to cache line collision.
|
||||
void MacroAssembler::serialize_memory(Register thread, Register tmp) {
|
||||
movl(tmp, thread);
|
||||
shrl(tmp, os::get_serialize_page_shift_count());
|
||||
andl(tmp, (os::vm_page_size() - sizeof(int)));
|
||||
|
||||
Address index(noreg, tmp, Address::times_1);
|
||||
ExternalAddress page(os::get_memory_serialize_page());
|
||||
|
||||
// Size of store must match masking code above
|
||||
movl(as_Address(ArrayAddress(page, index)), tmp);
|
||||
}
|
||||
|
||||
void MacroAssembler::safepoint_poll(Label& slow_path, Register thread_reg, Register temp_reg) {
|
||||
if (SafepointMechanism::uses_thread_local_poll()) {
|
||||
#ifdef _LP64
|
||||
|
||||
@ -96,6 +96,7 @@ class MacroAssembler: public Assembler {
|
||||
|
||||
void null_check(Register reg, int offset = -1);
|
||||
static bool needs_explicit_null_check(intptr_t offset);
|
||||
static bool uses_implicit_null_check(void* address);
|
||||
|
||||
// Required platform-specific helpers for Label::patch_instructions.
|
||||
// They _shadow_ the declarations in AbstractAssembler, which are undefined.
|
||||
@ -644,9 +645,6 @@ class MacroAssembler: public Assembler {
|
||||
Register tmp,
|
||||
int offset);
|
||||
|
||||
// Support for serializing memory accesses between threads
|
||||
void serialize_memory(Register thread, Register tmp);
|
||||
|
||||
// If thread_reg is != noreg the code assumes the register passed contains
|
||||
// the thread (required on 64 bit).
|
||||
void safepoint_poll(Label& slow_path, Register thread_reg, Register temp_reg);
|
||||
|
||||
@ -24,6 +24,7 @@
|
||||
|
||||
#include "precompiled.hpp"
|
||||
#include "asm/macroAssembler.hpp"
|
||||
#include "code/compiledIC.hpp"
|
||||
#include "memory/resourceArea.hpp"
|
||||
#include "nativeInst_x86.hpp"
|
||||
#include "oops/oop.inline.hpp"
|
||||
@ -257,8 +258,8 @@ void NativeCall::set_destination_mt_safe(address dest) {
|
||||
debug_only(verify());
|
||||
// Make sure patching code is locked. No two threads can patch at the same
|
||||
// time but one may be executing this code.
|
||||
assert(Patching_lock->is_locked() ||
|
||||
SafepointSynchronize::is_at_safepoint(), "concurrent code patching");
|
||||
assert(Patching_lock->is_locked() || SafepointSynchronize::is_at_safepoint() ||
|
||||
CompiledICLocker::is_safe(instruction_address()), "concurrent code patching");
|
||||
// Both C1 and C2 should now be generating code which aligns the patched address
|
||||
// to be within a single cache line.
|
||||
bool is_aligned = ((uintptr_t)displacement_address() + 0) / cache_line_size ==
|
||||
|
||||
@ -2088,18 +2088,10 @@ nmethod* SharedRuntime::generate_native_wrapper(MacroAssembler* masm,
|
||||
// didn't see any synchronization is progress, and escapes.
|
||||
__ movl(Address(thread, JavaThread::thread_state_offset()), _thread_in_native_trans);
|
||||
|
||||
if (UseMembar) {
|
||||
// Force this write out before the read below
|
||||
__ membar(Assembler::Membar_mask_bits(
|
||||
Assembler::LoadLoad | Assembler::LoadStore |
|
||||
Assembler::StoreLoad | Assembler::StoreStore));
|
||||
} else {
|
||||
// Write serialization page so VM thread can do a pseudo remote membar.
|
||||
// We use the current thread pointer to calculate a thread specific
|
||||
// offset to write to within the page. This minimizes bus traffic
|
||||
// due to cache line collision.
|
||||
__ serialize_memory(thread, rcx);
|
||||
}
|
||||
// Force this write out before the read below
|
||||
__ membar(Assembler::Membar_mask_bits(
|
||||
Assembler::LoadLoad | Assembler::LoadStore |
|
||||
Assembler::StoreLoad | Assembler::StoreStore));
|
||||
|
||||
if (AlwaysRestoreFPU) {
|
||||
// Make sure the control word is correct.
|
||||
|
||||
@ -2560,18 +2560,10 @@ nmethod* SharedRuntime::generate_native_wrapper(MacroAssembler* masm,
|
||||
// didn't see any synchronization is progress, and escapes.
|
||||
__ movl(Address(r15_thread, JavaThread::thread_state_offset()), _thread_in_native_trans);
|
||||
|
||||
if (UseMembar) {
|
||||
// Force this write out before the read below
|
||||
__ membar(Assembler::Membar_mask_bits(
|
||||
Assembler::LoadLoad | Assembler::LoadStore |
|
||||
Assembler::StoreLoad | Assembler::StoreStore));
|
||||
} else {
|
||||
// Write serialization page so VM thread can do a pseudo remote membar.
|
||||
// We use the current thread pointer to calculate a thread specific
|
||||
// offset to write to within the page. This minimizes bus traffic
|
||||
// due to cache line collision.
|
||||
__ serialize_memory(r15_thread, rcx);
|
||||
}
|
||||
// Force this write out before the read below
|
||||
__ membar(Assembler::Membar_mask_bits(
|
||||
Assembler::LoadLoad | Assembler::LoadStore |
|
||||
Assembler::StoreLoad | Assembler::StoreStore));
|
||||
|
||||
Label after_transition;
|
||||
|
||||
|
||||
@ -1090,18 +1090,10 @@ address TemplateInterpreterGenerator::generate_native_entry(bool synchronized) {
|
||||
__ movl(Address(thread, JavaThread::thread_state_offset()),
|
||||
_thread_in_native_trans);
|
||||
|
||||
if (UseMembar) {
|
||||
// Force this write out before the read below
|
||||
__ membar(Assembler::Membar_mask_bits(
|
||||
Assembler::LoadLoad | Assembler::LoadStore |
|
||||
Assembler::StoreLoad | Assembler::StoreStore));
|
||||
} else {
|
||||
// Write serialization page so VM thread can do a pseudo remote membar.
|
||||
// We use the current thread pointer to calculate a thread specific
|
||||
// offset to write to within the page. This minimizes bus traffic
|
||||
// due to cache line collision.
|
||||
__ serialize_memory(thread, rcx);
|
||||
}
|
||||
// Force this write out before the read below
|
||||
__ membar(Assembler::Membar_mask_bits(
|
||||
Assembler::LoadLoad | Assembler::LoadStore |
|
||||
Assembler::StoreLoad | Assembler::StoreStore));
|
||||
|
||||
#ifndef _LP64
|
||||
if (AlwaysRestoreFPU) {
|
||||
|
||||
@ -9263,6 +9263,18 @@ instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
|
||||
%}
|
||||
|
||||
// And Memory with Register
|
||||
instruct andB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
|
||||
%{
|
||||
match(Set dst (StoreB dst (AndI (LoadB dst) src)));
|
||||
effect(KILL cr);
|
||||
|
||||
ins_cost(150);
|
||||
format %{ "andb $dst, $src\t# byte" %}
|
||||
opcode(0x20);
|
||||
ins_encode(REX_breg_mem(src, dst), OpcP, reg_mem(src, dst));
|
||||
ins_pipe(ialu_mem_reg);
|
||||
%}
|
||||
|
||||
instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
|
||||
%{
|
||||
match(Set dst (StoreI dst (AndI (LoadI dst) src)));
|
||||
@ -9444,6 +9456,18 @@ instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
|
||||
%}
|
||||
|
||||
// Or Memory with Register
|
||||
instruct orB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
|
||||
%{
|
||||
match(Set dst (StoreB dst (OrI (LoadB dst) src)));
|
||||
effect(KILL cr);
|
||||
|
||||
ins_cost(150);
|
||||
format %{ "orb $dst, $src\t# byte" %}
|
||||
opcode(0x08);
|
||||
ins_encode(REX_breg_mem(src, dst), OpcP, reg_mem(src, dst));
|
||||
ins_pipe(ialu_mem_reg);
|
||||
%}
|
||||
|
||||
instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
|
||||
%{
|
||||
match(Set dst (StoreI dst (OrI (LoadI dst) src)));
|
||||
@ -9520,6 +9544,18 @@ instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
|
||||
%}
|
||||
|
||||
// Xor Memory with Register
|
||||
instruct xorB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
|
||||
%{
|
||||
match(Set dst (StoreB dst (XorI (LoadB dst) src)));
|
||||
effect(KILL cr);
|
||||
|
||||
ins_cost(150);
|
||||
format %{ "xorb $dst, $src\t# byte" %}
|
||||
opcode(0x30);
|
||||
ins_encode(REX_breg_mem(src, dst), OpcP, reg_mem(src, dst));
|
||||
ins_pipe(ialu_mem_reg);
|
||||
%}
|
||||
|
||||
instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
|
||||
%{
|
||||
match(Set dst (StoreI dst (XorI (LoadI dst) src)));
|
||||
@ -11889,9 +11925,9 @@ instruct compB_mem_imm(rFlagsReg cr, memory mem, immI8 imm)
|
||||
ins_pipe(ialu_cr_reg_mem);
|
||||
%}
|
||||
|
||||
instruct testB_mem_imm(rFlagsReg cr, memory mem, immI8 imm, immI0 zero)
|
||||
instruct testUB_mem_imm(rFlagsReg cr, memory mem, immU8 imm, immI0 zero)
|
||||
%{
|
||||
match(Set cr (CmpI (AndI (LoadB mem) imm) zero));
|
||||
match(Set cr (CmpI (AndI (LoadUB mem) imm) zero));
|
||||
|
||||
ins_cost(125);
|
||||
format %{ "testb $mem, $imm" %}
|
||||
|
||||
@ -47,6 +47,7 @@ class MacroAssembler : public Assembler {
|
||||
void align(int modulus);
|
||||
void bang_stack_with_offset(int offset);
|
||||
bool needs_explicit_null_check(intptr_t offset);
|
||||
bool uses_implicit_null_check(void* address);
|
||||
RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
|
||||
Register tmp, int offset);
|
||||
public:
|
||||
|
||||
@ -381,7 +381,7 @@ int CppInterpreter::native_entry(Method* method, intptr_t UNUSED, TRAPS) {
|
||||
|
||||
// Handle safepoint operations, pending suspend requests,
|
||||
// and pending asynchronous exceptions.
|
||||
if (SafepointMechanism::poll(thread) ||
|
||||
if (SafepointMechanism::should_block(thread) ||
|
||||
thread->has_special_condition_for_native_trans()) {
|
||||
JavaThread::check_special_condition_for_native_trans(thread);
|
||||
CHECK_UNHANDLED_OOPS_ONLY(thread->clear_unhandled_oops());
|
||||
@ -513,7 +513,7 @@ int CppInterpreter::accessor_entry(Method* method, intptr_t UNUSED, TRAPS) {
|
||||
intptr_t *locals = stack->sp();
|
||||
|
||||
// Drop into the slow path if we need a safepoint check
|
||||
if (SafepointMechanism::poll(THREAD)) {
|
||||
if (SafepointMechanism::should_block(THREAD)) {
|
||||
return normal_entry(method, 0, THREAD);
|
||||
}
|
||||
|
||||
@ -645,7 +645,7 @@ int CppInterpreter::empty_entry(Method* method, intptr_t UNUSED, TRAPS) {
|
||||
ZeroStack *stack = thread->zero_stack();
|
||||
|
||||
// Drop into the slow path if we need a safepoint check
|
||||
if (SafepointMechanism::poll(THREAD)) {
|
||||
if (SafepointMechanism::should_block(THREAD)) {
|
||||
return normal_entry(method, 0, THREAD);
|
||||
}
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2000, 2017, Oracle and/or its affiliates. All rights reserved.
|
||||
* Copyright (c) 2000, 2018, Oracle and/or its affiliates. All rights reserved.
|
||||
* Copyright 2007, 2008, 2009, 2010, 2011 Red Hat, Inc.
|
||||
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
|
||||
*
|
||||
@ -69,8 +69,6 @@ define_pd_global(intx, StackReservedPages, DEFAULT_STACK_RESERVED_PAGES);
|
||||
define_pd_global(bool, RewriteBytecodes, true);
|
||||
define_pd_global(bool, RewriteFrequentPairs, true);
|
||||
|
||||
define_pd_global(bool, UseMembar, true);
|
||||
|
||||
// GC Ergo Flags
|
||||
define_pd_global(size_t, CMSYoungGenPerWorker, 16*M); // default max size of CMS young gen, per GC worker thread
|
||||
|
||||
|
||||
@ -5956,14 +5956,6 @@ int os::compare_file_modified_times(const char* file1, const char* file2) {
|
||||
|
||||
#ifndef PRODUCT
|
||||
|
||||
#define test_log(...) \
|
||||
do { \
|
||||
if (VerboseInternalVMTests) { \
|
||||
tty->print_cr(__VA_ARGS__); \
|
||||
tty->flush(); \
|
||||
} \
|
||||
} while (false)
|
||||
|
||||
class TestReserveMemorySpecial : AllStatic {
|
||||
public:
|
||||
static void small_page_write(void* addr, size_t size) {
|
||||
@ -5980,8 +5972,6 @@ class TestReserveMemorySpecial : AllStatic {
|
||||
return;
|
||||
}
|
||||
|
||||
test_log("test_reserve_memory_special_huge_tlbfs_only(" SIZE_FORMAT ")", size);
|
||||
|
||||
char* addr = os::Linux::reserve_memory_special_huge_tlbfs_only(size, NULL, false);
|
||||
|
||||
if (addr != NULL) {
|
||||
@ -6040,15 +6030,10 @@ class TestReserveMemorySpecial : AllStatic {
|
||||
::munmap(mapping1, mapping_size);
|
||||
|
||||
// Case 1
|
||||
test_log("%s, req_addr NULL:", __FUNCTION__);
|
||||
test_log("size align result");
|
||||
|
||||
for (int i = 0; i < num_sizes; i++) {
|
||||
const size_t size = sizes[i];
|
||||
for (size_t alignment = ag; is_aligned(size, alignment); alignment *= 2) {
|
||||
char* p = os::Linux::reserve_memory_special_huge_tlbfs_mixed(size, alignment, NULL, false);
|
||||
test_log(SIZE_FORMAT_HEX " " SIZE_FORMAT_HEX " -> " PTR_FORMAT " %s",
|
||||
size, alignment, p2i(p), (p != NULL ? "" : "(failed)"));
|
||||
if (p != NULL) {
|
||||
assert(is_aligned(p, alignment), "must be");
|
||||
small_page_write(p, size);
|
||||
@ -6058,17 +6043,11 @@ class TestReserveMemorySpecial : AllStatic {
|
||||
}
|
||||
|
||||
// Case 2
|
||||
test_log("%s, req_addr non-NULL:", __FUNCTION__);
|
||||
test_log("size align req_addr result");
|
||||
|
||||
for (int i = 0; i < num_sizes; i++) {
|
||||
const size_t size = sizes[i];
|
||||
for (size_t alignment = ag; is_aligned(size, alignment); alignment *= 2) {
|
||||
char* const req_addr = align_up(mapping1, alignment);
|
||||
char* p = os::Linux::reserve_memory_special_huge_tlbfs_mixed(size, alignment, req_addr, false);
|
||||
test_log(SIZE_FORMAT_HEX " " SIZE_FORMAT_HEX " " PTR_FORMAT " -> " PTR_FORMAT " %s",
|
||||
size, alignment, p2i(req_addr), p2i(p),
|
||||
((p != NULL ? (p == req_addr ? "(exact match)" : "") : "(failed)")));
|
||||
if (p != NULL) {
|
||||
assert(p == req_addr, "must be");
|
||||
small_page_write(p, size);
|
||||
@ -6078,16 +6057,11 @@ class TestReserveMemorySpecial : AllStatic {
|
||||
}
|
||||
|
||||
// Case 3
|
||||
test_log("%s, req_addr non-NULL with preexisting mapping:", __FUNCTION__);
|
||||
test_log("size align req_addr result");
|
||||
|
||||
for (int i = 0; i < num_sizes; i++) {
|
||||
const size_t size = sizes[i];
|
||||
for (size_t alignment = ag; is_aligned(size, alignment); alignment *= 2) {
|
||||
char* const req_addr = align_up(mapping2, alignment);
|
||||
char* p = os::Linux::reserve_memory_special_huge_tlbfs_mixed(size, alignment, req_addr, false);
|
||||
test_log(SIZE_FORMAT_HEX " " SIZE_FORMAT_HEX " " PTR_FORMAT " -> " PTR_FORMAT " %s",
|
||||
size, alignment, p2i(req_addr), p2i(p), ((p != NULL ? "" : "(failed)")));
|
||||
// as the area around req_addr contains already existing mappings, the API should always
|
||||
// return NULL (as per contract, it cannot return another address)
|
||||
assert(p == NULL, "must be");
|
||||
@ -6112,8 +6086,6 @@ class TestReserveMemorySpecial : AllStatic {
|
||||
return;
|
||||
}
|
||||
|
||||
test_log("test_reserve_memory_special_shm(" SIZE_FORMAT ", " SIZE_FORMAT ")", size, alignment);
|
||||
|
||||
char* addr = os::Linux::reserve_memory_special_shm(size, alignment, NULL, false);
|
||||
|
||||
if (addr != NULL) {
|
||||
|
||||
@ -130,11 +130,6 @@ public:
|
||||
#endif
|
||||
};
|
||||
|
||||
// On POSIX platforms the signal handler is global so we just do the write.
|
||||
static void write_memory_serialize_page_with_handler(JavaThread* thread) {
|
||||
write_memory_serialize_page(thread);
|
||||
}
|
||||
|
||||
/*
|
||||
* Crash protection for the watcher thread. Wrap the callback
|
||||
* with a sigsetjmp and in case of a SIGSEGV/SIGBUS we siglongjmp
|
||||
|
||||
@ -2414,23 +2414,6 @@ LONG WINAPI topLevelExceptionFilter(struct _EXCEPTION_POINTERS* exceptionInfo) {
|
||||
}
|
||||
#endif // _WIN64
|
||||
|
||||
// Check to see if we caught the safepoint code in the
|
||||
// process of write protecting the memory serialization page.
|
||||
// It write enables the page immediately after protecting it
|
||||
// so just return.
|
||||
if (exception_code == EXCEPTION_ACCESS_VIOLATION) {
|
||||
if (t != NULL && t->is_Java_thread()) {
|
||||
JavaThread* thread = (JavaThread*) t;
|
||||
PEXCEPTION_RECORD exceptionRecord = exceptionInfo->ExceptionRecord;
|
||||
address addr = (address) exceptionRecord->ExceptionInformation[1];
|
||||
if (os::is_memory_serialize_page(thread, addr)) {
|
||||
// Block current thread until the memory serialize page permission restored.
|
||||
os::block_on_serialize_page_trap();
|
||||
return EXCEPTION_CONTINUE_EXECUTION;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if ((exception_code == EXCEPTION_ACCESS_VIOLATION) &&
|
||||
VM_Version::is_cpuinfo_segv_addr(pc)) {
|
||||
// Verify that OS save/restore AVX registers.
|
||||
@ -2509,7 +2492,7 @@ LONG WINAPI topLevelExceptionFilter(struct _EXCEPTION_POINTERS* exceptionInfo) {
|
||||
#endif
|
||||
{
|
||||
// Null pointer exception.
|
||||
if (!MacroAssembler::needs_explicit_null_check((intptr_t)addr)) {
|
||||
if (MacroAssembler::uses_implicit_null_check((void*)addr)) {
|
||||
address stub = SharedRuntime::continuation_for_implicit_exception(thread, pc, SharedRuntime::IMPLICIT_NULL);
|
||||
if (stub != NULL) return Handle_Exception(exceptionInfo, stub);
|
||||
}
|
||||
@ -5330,22 +5313,6 @@ bool os::find(address addr, outputStream* st) {
|
||||
return result;
|
||||
}
|
||||
|
||||
LONG WINAPI os::win32::serialize_fault_filter(struct _EXCEPTION_POINTERS* e) {
|
||||
DWORD exception_code = e->ExceptionRecord->ExceptionCode;
|
||||
|
||||
if (exception_code == EXCEPTION_ACCESS_VIOLATION) {
|
||||
JavaThread* thread = JavaThread::current();
|
||||
PEXCEPTION_RECORD exceptionRecord = e->ExceptionRecord;
|
||||
address addr = (address) exceptionRecord->ExceptionInformation[1];
|
||||
|
||||
if (os::is_memory_serialize_page(thread, addr)) {
|
||||
return EXCEPTION_CONTINUE_EXECUTION;
|
||||
}
|
||||
}
|
||||
|
||||
return EXCEPTION_CONTINUE_SEARCH;
|
||||
}
|
||||
|
||||
static jint initSock() {
|
||||
WSADATA wsadata;
|
||||
|
||||
@ -5557,12 +5524,8 @@ char* os::build_agent_function_name(const char *sym_name, const char *lib_name,
|
||||
// that is reported is when the test tries to allocate at a particular location but gets a
|
||||
// different valid one. A NULL return value at this point is not considered an error but may
|
||||
// be legitimate.
|
||||
// If -XX:+VerboseInternalVMTests is enabled, print some explanatory messages.
|
||||
void TestReserveMemorySpecial_test() {
|
||||
if (!UseLargePages) {
|
||||
if (VerboseInternalVMTests) {
|
||||
tty->print("Skipping test because large pages are disabled");
|
||||
}
|
||||
return;
|
||||
}
|
||||
// save current value of globals
|
||||
@ -5576,10 +5539,6 @@ void TestReserveMemorySpecial_test() {
|
||||
const size_t large_allocation_size = os::large_page_size() * 4;
|
||||
char* result = os::reserve_memory_special(large_allocation_size, os::large_page_size(), NULL, false);
|
||||
if (result == NULL) {
|
||||
if (VerboseInternalVMTests) {
|
||||
tty->print("Failed to allocate control block with size " SIZE_FORMAT ". Skipping remainder of test.",
|
||||
large_allocation_size);
|
||||
}
|
||||
} else {
|
||||
os::release_memory_special(result, large_allocation_size);
|
||||
|
||||
@ -5589,10 +5548,6 @@ void TestReserveMemorySpecial_test() {
|
||||
char* expected_location = result + os::large_page_size();
|
||||
char* actual_location = os::reserve_memory_special(expected_allocation_size, os::large_page_size(), expected_location, false);
|
||||
if (actual_location == NULL) {
|
||||
if (VerboseInternalVMTests) {
|
||||
tty->print("Failed to allocate any memory at " PTR_FORMAT " size " SIZE_FORMAT ". Skipping remainder of test.",
|
||||
expected_location, large_allocation_size);
|
||||
}
|
||||
} else {
|
||||
// release memory
|
||||
os::release_memory_special(actual_location, expected_allocation_size);
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
|
||||
* Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
|
||||
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
|
||||
*
|
||||
* This code is free software; you can redistribute it and/or modify it
|
||||
@ -108,9 +108,6 @@ class win32 {
|
||||
static address fast_jni_accessor_wrapper(BasicType);
|
||||
#endif
|
||||
|
||||
// filter function to ignore faults on serializations page
|
||||
static LONG WINAPI serialize_fault_filter(struct _EXCEPTION_POINTERS* e);
|
||||
|
||||
// Fast access to current thread
|
||||
protected:
|
||||
static int _thread_ptr_offset;
|
||||
@ -123,21 +120,6 @@ public:
|
||||
static inline int get_thread_ptr_offset() { return _thread_ptr_offset; }
|
||||
};
|
||||
|
||||
static void write_memory_serialize_page_with_handler(JavaThread* thread) {
|
||||
// Due to chained nature of SEH handlers we have to be sure
|
||||
// that our handler is always last handler before an attempt to write
|
||||
// into serialization page - it can fault if we access this page
|
||||
// right in the middle of protect/unprotect sequence by remote
|
||||
// membar logic.
|
||||
// __try/__except are very lightweight operations (only several
|
||||
// instructions not affecting control flow directly on x86)
|
||||
// so we can use it here, on very time critical path
|
||||
__try {
|
||||
write_memory_serialize_page(thread);
|
||||
} __except (win32::serialize_fault_filter((_EXCEPTION_POINTERS*)_exception_info()))
|
||||
{}
|
||||
}
|
||||
|
||||
/*
|
||||
* Crash protection for the watcher thread. Wrap the callback
|
||||
* with a __try { call() }
|
||||
|
||||
@ -409,7 +409,7 @@ JVM_handle_aix_signal(int sig, siginfo_t* info, void* ucVoid, int abort_if_unrec
|
||||
// SIGSEGV-based implicit null check in compiled code.
|
||||
else if (sig == SIGSEGV && ImplicitNullChecks &&
|
||||
CodeCache::contains((void*) pc) &&
|
||||
!MacroAssembler::needs_explicit_null_check((intptr_t) info->si_addr)) {
|
||||
MacroAssembler::uses_implicit_null_check(info->si_addr)) {
|
||||
if (TraceTraps) {
|
||||
tty->print_cr("trap: null_check at " INTPTR_FORMAT " (SIGSEGV)", pc);
|
||||
}
|
||||
@ -469,18 +469,6 @@ JVM_handle_aix_signal(int sig, siginfo_t* info, void* ucVoid, int abort_if_unrec
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
// Check to see if we caught the safepoint code in the
|
||||
// process of write protecting the memory serialization page.
|
||||
// It write enables the page immediately after protecting it
|
||||
// so we can just return to retry the write.
|
||||
if ((sig == SIGSEGV) &&
|
||||
os::is_memory_serialize_page(thread, addr)) {
|
||||
// Synchronization problem in the pseudo memory barrier code (bug id 6546278)
|
||||
// Block current thread until the memory serialize page permission restored.
|
||||
os::block_on_serialize_page_trap();
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
run_stub:
|
||||
@ -624,5 +612,3 @@ bool os::platform_print_native_stack(outputStream* st, void* context, char *buf,
|
||||
AixNativeCallstack::print_callstack_for_context(st, (const ucontext_t*)context, true, buf, (size_t) buf_size);
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 1999, 2017, Oracle and/or its affiliates. All rights reserved.
|
||||
* Copyright (c) 1999, 2018, Oracle and/or its affiliates. All rights reserved.
|
||||
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
|
||||
*
|
||||
* This code is free software; you can redistribute it and/or modify it
|
||||
@ -580,7 +580,7 @@ JVM_handle_bsd_signal(int sig,
|
||||
// 64-bit Darwin may also use a SIGBUS (seen with compressed oops).
|
||||
// Catching SIGBUS here prevents the implicit SIGBUS NULL check below from
|
||||
// being called, so only do so if the implicit NULL check is not necessary.
|
||||
} else if (sig == SIGBUS && MacroAssembler::needs_explicit_null_check((intptr_t)info->si_addr)) {
|
||||
} else if (sig == SIGBUS && !MacroAssembler::uses_implicit_null_check(info->si_addr)) {
|
||||
#else
|
||||
} else if (sig == SIGBUS /* && info->si_code == BUS_OBJERR */) {
|
||||
#endif
|
||||
@ -655,7 +655,7 @@ JVM_handle_bsd_signal(int sig,
|
||||
}
|
||||
#endif // AMD64
|
||||
} else if ((sig == SIGSEGV || sig == SIGBUS) &&
|
||||
!MacroAssembler::needs_explicit_null_check((intptr_t)info->si_addr)) {
|
||||
MacroAssembler::uses_implicit_null_check(info->si_addr)) {
|
||||
// Determination of interpreter/vtable stub/compiled code null exception
|
||||
stub = SharedRuntime::continuation_for_implicit_exception(thread, pc, SharedRuntime::IMPLICIT_NULL);
|
||||
}
|
||||
@ -674,17 +674,6 @@ JVM_handle_bsd_signal(int sig,
|
||||
stub = addr;
|
||||
}
|
||||
}
|
||||
|
||||
// Check to see if we caught the safepoint code in the
|
||||
// process of write protecting the memory serialization page.
|
||||
// It write enables the page immediately after protecting it
|
||||
// so we can just return to retry the write.
|
||||
if ((sig == SIGSEGV || sig == SIGBUS) &&
|
||||
os::is_memory_serialize_page(thread, (address) info->si_addr)) {
|
||||
// Block current thread until the memory serialize page permission restored.
|
||||
os::block_on_serialize_page_trap();
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
#ifndef AMD64
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2003, 2016, Oracle and/or its affiliates. All rights reserved.
|
||||
* Copyright (c) 2003, 2018, Oracle and/or its affiliates. All rights reserved.
|
||||
* Copyright 2007, 2008, 2009, 2010 Red Hat, Inc.
|
||||
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
|
||||
*
|
||||
@ -206,17 +206,6 @@ JVM_handle_bsd_signal(int sig,
|
||||
stub = addr;
|
||||
}
|
||||
}*/
|
||||
|
||||
// Check to see if we caught the safepoint code in the process
|
||||
// of write protecting the memory serialization page. It write
|
||||
// enables the page immediately after protecting it so we can
|
||||
// just return to retry the write.
|
||||
if ((sig == SIGSEGV || sig == SIGBUS) &&
|
||||
os::is_memory_serialize_page(thread, (address) info->si_addr)) {
|
||||
// Block current thread until permission is restored.
|
||||
os::block_on_serialize_page_trap();
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
// signal-chaining
|
||||
|
||||
@ -357,10 +357,15 @@ JVM_handle_linux_signal(int sig,
|
||||
}
|
||||
#endif
|
||||
|
||||
address addr = (address) info->si_addr;
|
||||
|
||||
// Make sure the high order byte is sign extended, as it may be masked away by the hardware.
|
||||
if ((uintptr_t(addr) & (uintptr_t(1) << 55)) != 0) {
|
||||
addr = address(uintptr_t(addr) | (uintptr_t(0xFF) << 56));
|
||||
}
|
||||
|
||||
// Handle ALL stack overflow variations here
|
||||
if (sig == SIGSEGV) {
|
||||
address addr = (address) info->si_addr;
|
||||
|
||||
// check if fault address is within thread stack
|
||||
if (thread->on_local_stack(addr)) {
|
||||
// stack overflow
|
||||
@ -456,7 +461,7 @@ JVM_handle_linux_signal(int sig,
|
||||
SharedRuntime::
|
||||
IMPLICIT_DIVIDE_BY_ZERO);
|
||||
} else if (sig == SIGSEGV &&
|
||||
!MacroAssembler::needs_explicit_null_check((intptr_t)info->si_addr)) {
|
||||
MacroAssembler::uses_implicit_null_check((void*)addr)) {
|
||||
// Determination of interpreter/vtable stub/compiled code null exception
|
||||
stub = SharedRuntime::continuation_for_implicit_exception(thread, pc, SharedRuntime::IMPLICIT_NULL);
|
||||
}
|
||||
@ -475,17 +480,6 @@ JVM_handle_linux_signal(int sig,
|
||||
stub = addr;
|
||||
}
|
||||
}
|
||||
|
||||
// Check to see if we caught the safepoint code in the
|
||||
// process of write protecting the memory serialization page.
|
||||
// It write enables the page immediately after protecting it
|
||||
// so we can just return to retry the write.
|
||||
if ((sig == SIGSEGV) &&
|
||||
os::is_memory_serialize_page(thread, (address) info->si_addr)) {
|
||||
// Block current thread until the memory serialize page permission restored.
|
||||
os::block_on_serialize_page_trap();
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
if (stub != NULL) {
|
||||
|
||||
@ -384,7 +384,8 @@ extern "C" int JVM_handle_linux_signal(int sig, siginfo_t* info,
|
||||
if (nm != NULL && nm->has_unsafe_access()) {
|
||||
unsafe_access = true;
|
||||
}
|
||||
} else if (sig == SIGSEGV && !MacroAssembler::needs_explicit_null_check((intptr_t)info->si_addr)) {
|
||||
} else if (sig == SIGSEGV &&
|
||||
MacroAssembler::uses_implicit_null_check(info->si_addr)) {
|
||||
// Determination of interpreter/vtable stub/compiled code null exception
|
||||
CodeBlob* cb = CodeCache::find_blob_unsafe(pc);
|
||||
if (cb != NULL) {
|
||||
@ -407,16 +408,6 @@ extern "C" int JVM_handle_linux_signal(int sig, siginfo_t* info,
|
||||
stub = addr;
|
||||
}
|
||||
}
|
||||
|
||||
// Check to see if we caught the safepoint code in the
|
||||
// process of write protecting the memory serialization page.
|
||||
// It write enables the page immediately after protecting it
|
||||
// so we can just return to retry the write.
|
||||
if (sig == SIGSEGV && os::is_memory_serialize_page(thread, (address) info->si_addr)) {
|
||||
// Block current thread until the memory serialize page permission restored.
|
||||
os::block_on_serialize_page_trap();
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
if (unsafe_access && stub == NULL) {
|
||||
@ -692,4 +683,3 @@ int os::extra_bang_size_in_bytes() {
|
||||
// ARM does not require an additional stack bang.
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
@ -431,7 +431,7 @@ JVM_handle_linux_signal(int sig,
|
||||
// SIGSEGV-based implicit null check in compiled code.
|
||||
else if (sig == SIGSEGV && ImplicitNullChecks &&
|
||||
CodeCache::contains((void*) pc) &&
|
||||
!MacroAssembler::needs_explicit_null_check((intptr_t) info->si_addr)) {
|
||||
MacroAssembler::uses_implicit_null_check(info->si_addr)) {
|
||||
if (TraceTraps) {
|
||||
tty->print_cr("trap: null_check at " INTPTR_FORMAT " (SIGSEGV)", p2i(pc));
|
||||
}
|
||||
@ -477,20 +477,6 @@ JVM_handle_linux_signal(int sig,
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
// Check to see if we caught the safepoint code in the
|
||||
// process of write protecting the memory serialization page.
|
||||
// It write enables the page immediately after protecting it
|
||||
// so we can just return to retry the write.
|
||||
if ((sig == SIGSEGV) &&
|
||||
// Si_addr may not be valid due to a bug in the linux-ppc64 kernel (see comment above).
|
||||
// Use is_memory_serialization instead of si_addr.
|
||||
((NativeInstruction*)pc)->is_memory_serialization(thread, ucVoid)) {
|
||||
// Synchronization problem in the pseudo memory barrier code (bug id 6546278)
|
||||
// Block current thread until the memory serialize page permission restored.
|
||||
os::block_on_serialize_page_trap();
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
if (stub != NULL) {
|
||||
|
||||
@ -418,7 +418,7 @@ JVM_handle_linux_signal(int sig,
|
||||
|
||||
else if (sig == SIGSEGV && ImplicitNullChecks &&
|
||||
CodeCache::contains((void*) pc) &&
|
||||
!MacroAssembler::needs_explicit_null_check((intptr_t) info->si_addr)) {
|
||||
MacroAssembler::uses_implicit_null_check(info->si_addr)) {
|
||||
if (TraceTraps) {
|
||||
tty->print_cr("trap: null_check at " INTPTR_FORMAT " (SIGSEGV)", p2i(pc));
|
||||
}
|
||||
@ -477,19 +477,6 @@ JVM_handle_linux_signal(int sig,
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
// Check to see if we caught the safepoint code in the
|
||||
// process of write protecting the memory serialization page.
|
||||
// It write enables the page immediately after protecting it
|
||||
// so we can just return to retry the write.
|
||||
// Info->si_addr need not be the exact address, it is only
|
||||
// guaranteed to be on the same page as the address that caused
|
||||
// the SIGSEGV.
|
||||
if ((sig == SIGSEGV) && !UseMembar &&
|
||||
(os::get_memory_serialize_page() ==
|
||||
(address)((uintptr_t)info->si_addr & ~(os::vm_page_size()-1)))) {
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
if (stub != NULL) {
|
||||
|
||||
@ -416,9 +416,9 @@ inline static bool checkFPFault(address pc, int code,
|
||||
return false;
|
||||
}
|
||||
|
||||
inline static bool checkNullPointer(address pc, intptr_t fault,
|
||||
inline static bool checkNullPointer(address pc, void* fault,
|
||||
JavaThread* thread, address* stub) {
|
||||
if (!MacroAssembler::needs_explicit_null_check(fault)) {
|
||||
if (MacroAssembler::uses_implicit_null_check(fault)) {
|
||||
// Determination of interpreter/vtable stub/compiled code null
|
||||
// exception
|
||||
*stub =
|
||||
@ -439,10 +439,6 @@ inline static bool checkFastJNIAccess(address pc, address* stub) {
|
||||
return false;
|
||||
}
|
||||
|
||||
inline static bool checkSerializePage(JavaThread* thread, address addr) {
|
||||
return os::is_memory_serialize_page(thread, addr);
|
||||
}
|
||||
|
||||
inline static bool checkZombie(sigcontext* uc, address* pc, address* stub) {
|
||||
if (nativeInstruction_at(*pc)->is_zombie()) {
|
||||
// zombie method (ld [%g0],%o7 instruction)
|
||||
@ -542,16 +538,6 @@ JVM_handle_linux_signal(int sig,
|
||||
pc = address(SIG_PC(uc));
|
||||
npc = address(SIG_NPC(uc));
|
||||
|
||||
// Check to see if we caught the safepoint code in the
|
||||
// process of write protecting the memory serialization page.
|
||||
// It write enables the page immediately after protecting it
|
||||
// so we can just return to retry the write.
|
||||
if ((sig == SIGSEGV) && checkSerializePage(thread, (address)info->si_addr)) {
|
||||
// Block current thread until the memory serialize page permission restored.
|
||||
os::block_on_serialize_page_trap();
|
||||
return 1;
|
||||
}
|
||||
|
||||
if (checkPrefetch(uc, pc)) {
|
||||
return 1;
|
||||
}
|
||||
@ -600,7 +586,7 @@ JVM_handle_linux_signal(int sig,
|
||||
}
|
||||
|
||||
if ((sig == SIGSEGV) &&
|
||||
checkNullPointer(pc, (intptr_t)info->si_addr, thread, &stub)) {
|
||||
checkNullPointer(pc, info->si_addr, thread, &stub)) {
|
||||
break;
|
||||
}
|
||||
} while (0);
|
||||
|
||||
@ -479,7 +479,7 @@ JVM_handle_linux_signal(int sig,
|
||||
}
|
||||
#endif // AMD64
|
||||
} else if (sig == SIGSEGV &&
|
||||
!MacroAssembler::needs_explicit_null_check((intptr_t)info->si_addr)) {
|
||||
MacroAssembler::uses_implicit_null_check(info->si_addr)) {
|
||||
// Determination of interpreter/vtable stub/compiled code null exception
|
||||
stub = SharedRuntime::continuation_for_implicit_exception(thread, pc, SharedRuntime::IMPLICIT_NULL);
|
||||
}
|
||||
@ -498,17 +498,6 @@ JVM_handle_linux_signal(int sig,
|
||||
stub = addr;
|
||||
}
|
||||
}
|
||||
|
||||
// Check to see if we caught the safepoint code in the
|
||||
// process of write protecting the memory serialization page.
|
||||
// It write enables the page immediately after protecting it
|
||||
// so we can just return to retry the write.
|
||||
if ((sig == SIGSEGV) &&
|
||||
os::is_memory_serialize_page(thread, (address) info->si_addr)) {
|
||||
// Block current thread until the memory serialize page permission restored.
|
||||
os::block_on_serialize_page_trap();
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
#ifndef AMD64
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2003, 2016, Oracle and/or its affiliates. All rights reserved.
|
||||
* Copyright (c) 2003, 2018, Oracle and/or its affiliates. All rights reserved.
|
||||
* Copyright 2007, 2008, 2009, 2010 Red Hat, Inc.
|
||||
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
|
||||
*
|
||||
@ -220,17 +220,6 @@ JVM_handle_linux_signal(int sig,
|
||||
stub = addr;
|
||||
}
|
||||
}*/
|
||||
|
||||
// Check to see if we caught the safepoint code in the process
|
||||
// of write protecting the memory serialization page. It write
|
||||
// enables the page immediately after protecting it so we can
|
||||
// just return to retry the write.
|
||||
if (sig == SIGSEGV &&
|
||||
os::is_memory_serialize_page(thread, (address) info->si_addr)) {
|
||||
// Block current thread until permission is restored.
|
||||
os::block_on_serialize_page_trap();
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
// signal-chaining
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 1999, 2017, Oracle and/or its affiliates. All rights reserved.
|
||||
* Copyright (c) 1999, 2018, Oracle and/or its affiliates. All rights reserved.
|
||||
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
|
||||
*
|
||||
* This code is free software; you can redistribute it and/or modify it
|
||||
@ -505,7 +505,7 @@ JVM_handle_solaris_signal(int sig, siginfo_t* info, void* ucVoid,
|
||||
}
|
||||
#endif // COMPILER2
|
||||
|
||||
else if (sig == SIGSEGV && info->si_code > 0 && !MacroAssembler::needs_explicit_null_check((intptr_t)info->si_addr)) {
|
||||
else if (sig == SIGSEGV && info->si_code > 0 && MacroAssembler::uses_implicit_null_check(info->si_addr)) {
|
||||
// Determination of interpreter/vtable stub/compiled code null exception
|
||||
stub = SharedRuntime::continuation_for_implicit_exception(thread, pc, SharedRuntime::IMPLICIT_NULL);
|
||||
}
|
||||
@ -519,17 +519,6 @@ JVM_handle_solaris_signal(int sig, siginfo_t* info, void* ucVoid,
|
||||
stub = addr;
|
||||
}
|
||||
}
|
||||
|
||||
// Check to see if we caught the safepoint code in the
|
||||
// process of write protecting the memory serialization page.
|
||||
// It write enables the page immediately after protecting it
|
||||
// so just return.
|
||||
if ((sig == SIGSEGV) &&
|
||||
os::is_memory_serialize_page(thread, (address)info->si_addr)) {
|
||||
// Block current thread until the memory serialize page permission restored.
|
||||
os::block_on_serialize_page_trap();
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
if (stub != NULL) {
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 1999, 2017, Oracle and/or its affiliates. All rights reserved.
|
||||
* Copyright (c) 1999, 2018, Oracle and/or its affiliates. All rights reserved.
|
||||
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
|
||||
*
|
||||
* This code is free software; you can redistribute it and/or modify it
|
||||
@ -579,7 +579,8 @@ JVM_handle_solaris_signal(int sig, siginfo_t* info, void* ucVoid,
|
||||
// QQQ It doesn't seem that we need to do this on x86 because we should be able
|
||||
// to return properly from the handler without this extra stuff on the back side.
|
||||
|
||||
else if (sig == SIGSEGV && info->si_code > 0 && !MacroAssembler::needs_explicit_null_check((intptr_t)info->si_addr)) {
|
||||
else if (sig == SIGSEGV && info->si_code > 0 &&
|
||||
MacroAssembler::uses_implicit_null_check(info->si_addr)) {
|
||||
// Determination of interpreter/vtable stub/compiled code null exception
|
||||
stub = SharedRuntime::continuation_for_implicit_exception(thread, pc, SharedRuntime::IMPLICIT_NULL);
|
||||
}
|
||||
@ -593,17 +594,6 @@ JVM_handle_solaris_signal(int sig, siginfo_t* info, void* ucVoid,
|
||||
stub = addr;
|
||||
}
|
||||
}
|
||||
|
||||
// Check to see if we caught the safepoint code in the
|
||||
// process of write protecting the memory serialization page.
|
||||
// It write enables the page immediately after protecting it
|
||||
// so we can just return to retry the write.
|
||||
if ((sig == SIGSEGV) &&
|
||||
os::is_memory_serialize_page(thread, (address)info->si_addr)) {
|
||||
// Block current thread until the memory serialize page permission restored.
|
||||
os::block_on_serialize_page_trap();
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
// Execution protection violation
|
||||
|
||||
@ -926,7 +926,7 @@ void AOTCodeHeap::cleanup_inline_caches() {
|
||||
continue; // Skip uninitialized entries.
|
||||
}
|
||||
AOTCompiledMethod* aot = _code_to_aot[index]._aot;
|
||||
aot->cleanup_inline_caches();
|
||||
aot->cleanup_inline_caches(false);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -75,10 +75,6 @@ address* AOTCompiledMethod::orig_pc_addr(const frame* fr) {
|
||||
return (address*) ((address)fr->unextended_sp() + _meta->orig_pc_offset());
|
||||
}
|
||||
|
||||
bool AOTCompiledMethod::do_unloading_oops(address low_boundary, BoolObjectClosure* is_alive) {
|
||||
return false;
|
||||
}
|
||||
|
||||
oop AOTCompiledMethod::oop_at(int index) const {
|
||||
if (index == 0) { // 0 is reserved
|
||||
return NULL;
|
||||
@ -352,7 +348,7 @@ void AOTCompiledMethod::log_identity(xmlStream* log) const {
|
||||
log->print(" aot='%2d'", _heap->dso_id());
|
||||
}
|
||||
|
||||
void AOTCompiledMethod::log_state_change(oop cause) const {
|
||||
void AOTCompiledMethod::log_state_change() const {
|
||||
if (LogCompilation) {
|
||||
ResourceMark m;
|
||||
if (xtty != NULL) {
|
||||
|
||||
@ -193,7 +193,7 @@ private:
|
||||
virtual int comp_level() const { return CompLevel_aot; }
|
||||
virtual address verified_entry_point() const { return _code + _meta->verified_entry_offset(); }
|
||||
virtual void log_identity(xmlStream* stream) const;
|
||||
virtual void log_state_change(oop cause = NULL) const;
|
||||
virtual void log_state_change() const;
|
||||
virtual bool make_entrant() NOT_TIERED({ ShouldNotReachHere(); return false; });
|
||||
virtual bool make_not_entrant() { return make_not_entrant_helper(not_entrant); }
|
||||
virtual bool make_not_used() { return make_not_entrant_helper(not_used); }
|
||||
@ -277,11 +277,6 @@ protected:
|
||||
CompiledStaticCall* compiledStaticCall_before(address addr) const;
|
||||
private:
|
||||
bool is_aot_runtime_stub() const { return _method == NULL; }
|
||||
|
||||
protected:
|
||||
virtual bool do_unloading_oops(address low_boundary, BoolObjectClosure* is_alive);
|
||||
virtual bool do_unloading_jvmci() { return false; }
|
||||
|
||||
};
|
||||
|
||||
class PltNativeCallWrapper: public NativeCallWrapper {
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
x
Reference in New Issue
Block a user