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8347343: RISC-V: Unchecked zicntr csr reads

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Reviewed-by: fyang, mli
This commit is contained in:
Robbin Ehn 2025-01-18 09:19:21 +00:00
parent ca8ba5c890
commit 1f0efc0091
3 changed files with 18 additions and 27 deletions
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19
src/hotspot/cpu/riscv/macroAssembler_riscv.cpp
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@ -1333,22 +1333,11 @@ void MacroAssembler::cmov_gtu(Register cmp1, Register cmp2, Register dst, Regist
#undef INSN
#define INSN(NAME, CSR) \
void MacroAssembler::NAME(Register Rd) { \
csrr(Rd, CSR); \
}
INSN(rdinstret, CSR_INSTRET);
INSN(rdcycle, CSR_CYCLE);
INSN(rdtime, CSR_TIME);
INSN(frcsr, CSR_FCSR);
INSN(frrm, CSR_FRM);
INSN(frflags, CSR_FFLAGS);
#undef INSN
void MacroAssembler::csrr(Register Rd, unsigned csr) {
// These three are specified in zicntr and are unused.
// Before adding use-cases add the appropriate hwprobe and flag.
assert(csr != CSR_INSTRET && csr != CSR_CYCLE && csr != CSR_TIME,
"Not intended for use without enabling zicntr.");
csrrs(Rd, csr, x0);
}

25
src/hotspot/cpu/riscv/macroAssembler_riscv.hpp
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@ -626,9 +626,6 @@ class MacroAssembler: public Assembler {
}
// Control and status pseudo instructions
void rdinstret(Register Rd); // read instruction-retired counter
void rdcycle(Register Rd); // read cycle counter
void rdtime(Register Rd); // read time
void csrr(Register Rd, unsigned csr); // read csr
void csrw(unsigned csr, Register Rs); // write csr
void csrs(unsigned csr, Register Rs); // set bits in csr
@ -636,19 +633,23 @@ class MacroAssembler: public Assembler {
void csrwi(unsigned csr, unsigned imm);
void csrsi(unsigned csr, unsigned imm);
void csrci(unsigned csr, unsigned imm);
void frcsr(Register Rd); // read float-point csr
void fscsr(Register Rd, Register Rs); // swap float-point csr
void fscsr(Register Rs); // write float-point csr
void frrm(Register Rd); // read float-point rounding mode
void fsrm(Register Rd, Register Rs); // swap float-point rounding mode
void fsrm(Register Rs); // write float-point rounding mode
void frcsr(Register Rd) { csrr(Rd, CSR_FCSR); }; // read float-point csr
void fscsr(Register Rd, Register Rs); // swap float-point csr
void fscsr(Register Rs); // write float-point csr
void frrm(Register Rd) { csrr(Rd, CSR_FRM); }; // read float-point rounding mode
void fsrm(Register Rd, Register Rs); // swap float-point rounding mode
void fsrm(Register Rs); // write float-point rounding mode
void fsrmi(Register Rd, unsigned imm);
void fsrmi(unsigned imm);
void frflags(Register Rd); // read float-point exception flags
void fsflags(Register Rd, Register Rs); // swap float-point exception flags
void fsflags(Register Rs); // write float-point exception flags
void frflags(Register Rd) { csrr(Rd, CSR_FFLAGS); }; // read float-point exception flags
void fsflags(Register Rd, Register Rs); // swap float-point exception flags
void fsflags(Register Rs); // write float-point exception flags
void fsflagsi(Register Rd, unsigned imm);
void fsflagsi(unsigned imm);
// Requires Zicntr
void rdinstret(Register Rd) { csrr(Rd, CSR_INSTRET); }; // read instruction-retired counter
void rdcycle(Register Rd) { csrr(Rd, CSR_CYCLE); }; // read cycle counter
void rdtime(Register Rd) { csrr(Rd, CSR_TIME); }; // read time
// Restore cpu control state after JNI call
void restore_cpu_control_state_after_jni(Register tmp);

1
src/hotspot/cpu/riscv/vm_version_riscv.hpp
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@ -158,6 +158,7 @@ class VM_Version : public Abstract_VM_Version {
decl(ext_Zcb , "Zcb" , RV_NO_FLAG_BIT, true , UPDATE_DEFAULT(UseZcb)) \
decl(ext_Zfh , "Zfh" , RV_NO_FLAG_BIT, true , UPDATE_DEFAULT(UseZfh)) \
decl(ext_Zicsr , "Zicsr" , RV_NO_FLAG_BIT, true , NO_UPDATE_DEFAULT) \
decl(ext_Zicntr , "Zicntr" , RV_NO_FLAG_BIT, true , NO_UPDATE_DEFAULT) \
decl(ext_Zifencei , "Zifencei" , RV_NO_FLAG_BIT, true , NO_UPDATE_DEFAULT) \
decl(ext_Zic64b , "Zic64b" , RV_NO_FLAG_BIT, true , UPDATE_DEFAULT(UseZic64b)) \
decl(ext_Ztso , "Ztso" , RV_NO_FLAG_BIT, true , UPDATE_DEFAULT(UseZtso)) \