8354213: Restore pointless unicode characters to ASCII
Reviewed-by: naoto, erikj, iris
This commit is contained in:
Magnus Ihse Bursie
parent
776e1cf1df
commit
4a242e3a65
@ -1,3 +1,3 @@
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# Contributing to the JDK
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Please see the [OpenJDK Developers’ Guide](https://openjdk.org/guide/).
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Please see the [OpenJDK Developers' Guide](https://openjdk.org/guide/).
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@ -106,7 +106,7 @@ Prefer having checks inside test code.
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Not only does having test logic outside, e.g. verification method,
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depending on asserts in product code contradict with several items
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above but also decreases test’s readability and stability. It is much
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above but also decreases test's readability and stability. It is much
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easier to understand that a test is testing when all testing logic is
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located inside a test or nearby in shared test libraries. As a rule of
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thumb, the closer a check to a test, the better.
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@ -119,7 +119,7 @@ Prefer `EXPECT` over `ASSERT` if possible.
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This is related to the [informativeness](#informativeness) property of
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tests, information for other checks can help to better localize a
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defect’s root-cause. One should use `ASSERT` if it is impossible to
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defect's root-cause. One should use `ASSERT` if it is impossible to
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continue test execution or if it does not make much sense. Later in
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the text, `EXPECT` forms will be used to refer to both
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`ASSERT/EXPECT`.
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@ -160,7 +160,7 @@ value of the difference between `v1` and `v2` is not greater than `eps`.
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Use string special macros for C strings comparisons.
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`EXPECT_EQ` just compares pointers’ values, which is hardly what one
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`EXPECT_EQ` just compares pointers' values, which is hardly what one
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wants comparing C strings. GoogleTest provides `EXPECT_STREQ` and
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`EXPECT_STRNE` macros to compare C string contents. There are also
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case-insensitive versions `EXPECT_STRCASEEQ`, `EXPECT_STRCASENE`.
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@ -226,7 +226,7 @@ subsystem, etc.
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This naming scheme helps to find tests, filter them and simplifies
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test failure analysis. For example, class `Foo` - test group `Foo`,
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compiler logging subsystem - test group `CompilerLogging`, G1 GC — test
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compiler logging subsystem - test group `CompilerLogging`, G1 GC - test
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group `G1GC`, and so forth.
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### Filename
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@ -287,7 +287,7 @@ Fixture classes should be named after tested classes, subsystems, etc
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All test purpose friends should have either `Test` or `Testable` suffix.
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It greatly simplifies understanding of friendship’s purpose and allows
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It greatly simplifies understanding of friendship's purpose and allows
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statically check that private members are not exposed unexpectedly.
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Having `FooTest` as a friend of `Foo` without any comments will be
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understood as a necessary evil to get testability.
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@ -397,7 +397,7 @@ and filter out inapplicable tests.
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Restore changed flags.
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It is quite common for tests to configure JVM in a certain way
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changing flags’ values. GoogleTest provides two ways to set up
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changing flags' values. GoogleTest provides two ways to set up
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environment before a test and restore it afterward: using either
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constructor and destructor or `SetUp` and `TearDown` functions. Both ways
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require to use a test fixture class, which sometimes is too wordy. The
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@ -406,7 +406,7 @@ be used in such cases to restore/set values.
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Caveats:
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* Changing a flag’s value could break the invariants between flags' values and hence could lead to unexpected/unsupported JVM state.
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* Changing a flag's value could break the invariants between flags' values and hence could lead to unexpected/unsupported JVM state.
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* `FLAG_SET_*` macros can change more than one flag (in order to
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maintain invariants) so it is hard to predict what flags will be
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@ -87,7 +87,7 @@ void RangeCheckStub::emit_code(LIR_Assembler* ce) {
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__ mv(t1, _array->as_pointer_register());
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stub_id = C1StubId::throw_range_check_failed_id;
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}
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// t0 and t1 are used as args in generate_exception_throw，
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// t0 and t1 are used as args in generate_exception_throw,
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// so use x1/ra as the tmp register for rt_call.
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__ rt_call(Runtime1::entry_for(stub_id), ra);
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ce->add_call_info_here(_info);
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@ -275,7 +275,7 @@ void BarrierSetAssembler::nmethod_entry_barrier(MacroAssembler* masm, Label* slo
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// order, while allowing other independent instructions to be reordered.
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// Note: This may be slower than using a membar(load|load) (fence r,r).
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// Because processors will not start the second load until the first comes back.
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// This means you can’t overlap the two loads,
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// This means you can't overlap the two loads,
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// which is stronger than needed for ordering (stronger than TSO).
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__ srli(ra, t0, 32);
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__ orr(t1, t1, ra);
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@ -670,9 +670,9 @@ class MacroAssembler: public Assembler {
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// JALR, return address stack updates:
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// | rd is x1/x5 | rs1 is x1/x5 | rd=rs1 | RAS action
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// | ----------- | ------------ | ------ |-------------
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// | No | No | — | None
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// | No | Yes | — | Pop
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// | Yes | No | — | Push
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// | No | No | - | None
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// | No | Yes | - | Pop
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// | Yes | No | - | Push
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// | Yes | Yes | No | Pop, then push
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// | Yes | Yes | Yes | Push
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//
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@ -62,7 +62,7 @@ address Disassembler::decode_instruction0(address here, outputStream * st, addre
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if (Assembler::is_z_nop((long)instruction_2bytes)) {
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#if 1
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st->print("nop "); // fill up to operand column, leads to better code comment alignment
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st->print("nop "); // fill up to operand column, leads to better code comment alignment
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next = here + 2;
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#else
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// Compact disassembler output. Does not work the easy way.
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@ -76,7 +76,7 @@ address Disassembler::decode_instruction0(address here, outputStream * st, addre
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instruction_2bytes = *(uint16_t*)(here+2*n_nops);
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}
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if (n_nops <= 4) { // do not group few subsequent nops
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st->print("nop "); // fill up to operand column, leads to better code comment alignment
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st->print("nop "); // fill up to operand column, leads to better code comment alignment
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next = here + 2;
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} else {
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st->print("nop count=%d", n_nops);
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@ -6581,7 +6581,7 @@ instruct mulHiL_reg_reg(revenRegL Rdst, roddRegL Rsrc1, iRegL Rsrc2, iRegL Rtmp1
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Register tmp1 = $Rtmp1$$Register;
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Register tmp2 = $Rdst$$Register;
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// z/Architecture has only unsigned multiply (64 * 64 -> 128).
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// implementing mulhs(a,b) = mulhu(a,b) – (a & (b>>63)) – (b & (a>>63))
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// implementing mulhs(a,b) = mulhu(a,b) - (a & (b>>63)) - (b & (a>>63))
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__ z_srag(tmp2, src1, 63); // a>>63
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__ z_srag(tmp1, src2, 63); // b>>63
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__ z_ngr(tmp2, src2); // b & (a>>63)
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@ -332,7 +332,7 @@ typedef struct { /* component perfstat_cpu_t from AIX 7.2 documentation */
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u_longlong_t busy_stolen_purr; /* Number of busy cycles stolen by the hypervisor from a dedicated partition. */
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u_longlong_t busy_stolen_spurr; /* Number of busy spurr cycles stolen by the hypervisor from a dedicated partition.*/
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u_longlong_t shcpus_in_sys; /* Number of physical processors allocated for shared processor use, across all shared processors pools. */
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u_longlong_t entitled_pool_capacity; /* Entitled processor capacity of partition’s pool. */
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u_longlong_t entitled_pool_capacity; /* Entitled processor capacity of partition's pool. */
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u_longlong_t pool_max_time; /* Summation of maximum time that can be consumed by the pool (nanoseconds). */
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u_longlong_t pool_busy_time; /* Summation of busy (nonidle) time accumulated across all partitions in the pool (nanoseconds). */
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u_longlong_t pool_scaled_busy_time; /* Scaled summation of busy (nonidle) time accumulated across all partitions in the pool (nanoseconds). */
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@ -295,7 +295,7 @@ DECLARE_FUNC(aarch64_atomic_cmpxchg_8_relaxed_default_impl):
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ret
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/* Emit .note.gnu.property section in case of PAC or BTI being enabled.
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* For more details see "ELF for the Arm® 64-bit Architecture (AArch64)".
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* For more details see "ELF for the Arm(R) 64-bit Architecture (AArch64)".
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* https://github.com/ARM-software/abi-aa/blob/main/aaelf64/aaelf64.rst
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*/
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#ifdef __ARM_FEATURE_BTI_DEFAULT
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@ -269,7 +269,7 @@ bwd_copy_drain:
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ret
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/* Emit .note.gnu.property section in case of PAC or BTI being enabled.
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* For more details see "ELF for the Arm® 64-bit Architecture (AArch64)".
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* For more details see "ELF for the Arm(R) 64-bit Architecture (AArch64)".
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* https://github.com/ARM-software/abi-aa/blob/main/aaelf64/aaelf64.rst
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*/
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#ifdef __ARM_FEATURE_BTI_DEFAULT
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@ -50,7 +50,7 @@ DECLARE_FUNC(_SafeFetchN_continuation):
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ret
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/* Emit .note.gnu.property section in case of PAC or BTI being enabled.
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* For more details see "ELF for the Arm® 64-bit Architecture (AArch64)".
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* For more details see "ELF for the Arm(R) 64-bit Architecture (AArch64)".
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* https://github.com/ARM-software/abi-aa/blob/main/aaelf64/aaelf64.rst
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*/
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#ifdef __ARM_FEATURE_BTI_DEFAULT
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@ -46,7 +46,7 @@ DECLARE_FUNC(_ZN10JavaThread25aarch64_get_thread_helperEv):
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.size _ZN10JavaThread25aarch64_get_thread_helperEv, .-_ZN10JavaThread25aarch64_get_thread_helperEv
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/* Emit .note.gnu.property section in case of PAC or BTI being enabled.
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* For more details see "ELF for the Arm® 64-bit Architecture (AArch64)".
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* For more details see "ELF for the Arm(R) 64-bit Architecture (AArch64)".
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* https://github.com/ARM-software/abi-aa/blob/main/aaelf64/aaelf64.rst
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*/
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#ifdef __ARM_FEATURE_BTI_DEFAULT
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@ -54,13 +54,13 @@ inline void OrderAccess::fence() {
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}
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inline void OrderAccess::cross_modify_fence_impl() {
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// From 3 “Zifencei” Instruction-Fetch Fence, Version 2.0
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// From 3 "Zifencei" Instruction-Fetch Fence, Version 2.0
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// "RISC-V does not guarantee that stores to instruction memory will be made
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// visible to instruction fetches on a RISC-V hart until that hart executes a
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// FENCE.I instruction. A FENCE.I instruction ensures that a subsequent
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// instruction fetch on a RISC-V hart will see any previous data stores
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// already visible to the same RISC-V hart. FENCE.I does not ensure that other
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// RISC-V harts’ instruction fetches will observe the local hart’s stores in a
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// RISC-V harts' instruction fetches will observe the local hart's stores in a
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// multiprocessor system."
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//
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// Hence to be able to use fence.i directly we need a kernel that supports
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@ -106,7 +106,7 @@ public:
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// within the archive (e.g., InstanceKlass::_name points to a Symbol in the archive). During dumping, we
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// built a bitmap that marks the locations of all these pointers (using ArchivePtrMarker, see comments above).
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//
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// The contents of the archive assumes that it’s mapped at the default SharedBaseAddress (e.g. 0x800000000).
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// The contents of the archive assumes that it's mapped at the default SharedBaseAddress (e.g. 0x800000000).
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// If the archive ends up being mapped at a different address (e.g. 0x810000000), SharedDataRelocator
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// is used to shift each marked pointer by a delta (0x10000000 in this example), so that it points to
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// the actually mapped location of the target object.
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@ -433,7 +433,7 @@ void Method::set_itable_index(int index) {
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// itable index should be the same as the runtime index.
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assert(_vtable_index == itable_index_max - index,
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"archived itable index is different from runtime index");
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return; // don’t write into the shared class
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return; // don't write into the shared class
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} else {
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_vtable_index = itable_index_max - index;
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}
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@ -70,7 +70,7 @@ public:
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~G1CardSetTest() { }
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static uint next_random(uint& seed, uint i) {
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// Park–Miller random number generator
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// Park-Miller random number generator
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seed = (seed * 279470273u) % 0xfffffffb;
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return (seed % i);
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}
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@ -82,7 +82,7 @@ void TestReserveMemorySpecial_test() {
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// Instead try reserving after the first reservation.
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expected_location = result + large_allocation_size;
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actual_location = os::reserve_memory_special(expected_allocation_size, os::large_page_size(), os::large_page_size(), expected_location, false);
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EXPECT_TRUE(actual_location != nullptr) << "Unexpected reservation failure, can’t verify correct location";
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EXPECT_TRUE(actual_location != nullptr) << "Unexpected reservation failure, can't verify correct location";
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EXPECT_TRUE(actual_location == expected_location) << "Reservation must be at requested location";
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MemoryReleaser m2(actual_location, os::large_page_size());
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@ -90,7 +90,7 @@ void TestReserveMemorySpecial_test() {
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const size_t alignment = os::large_page_size() * 2;
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const size_t new_large_size = alignment * 4;
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char* aligned_request = os::reserve_memory_special(new_large_size, alignment, os::large_page_size(), nullptr, false);
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EXPECT_TRUE(aligned_request != nullptr) << "Unexpected reservation failure, can’t verify correct alignment";
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EXPECT_TRUE(aligned_request != nullptr) << "Unexpected reservation failure, can't verify correct alignment";
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EXPECT_TRUE(is_aligned(aligned_request, alignment)) << "Returned address must be aligned";
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MemoryReleaser m3(aligned_request, new_large_size);
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}
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@ -191,7 +191,7 @@ class TestZGCCorrectBarrierElision {
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static void testAllocateThenAtomic(Inner i) {
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Outer o = new Outer();
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Common.blackhole(o);
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Common.field1VarHandle.getAndSet(o, i);
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Common.field1VarHandle.getAndSet(o, i);
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}
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@Test
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@ -199,14 +199,14 @@ class TestZGCCorrectBarrierElision {
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@IR(counts = { IRNode.Z_GET_AND_SET_P_WITH_BARRIER_FLAG, Common.REMAINING, "1" }, phase = CompilePhase.FINAL_CODE)
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static void testLoadThenAtomic(Outer o, Inner i) {
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Common.blackhole(o.field1);
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Common.field1VarHandle.getAndSet(o, i);
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Common.field1VarHandle.getAndSet(o, i);
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}
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@Test
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@IR(counts = { IRNode.Z_GET_AND_SET_P_WITH_BARRIER_FLAG, Common.REMAINING, "2" }, phase = CompilePhase.FINAL_CODE)
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static void testAtomicThenAtomicAnotherField(Outer o, Inner i) {
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Common.field1VarHandle.getAndSet(o, i);
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Common.field2VarHandle.getAndSet(o, i);
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Common.field1VarHandle.getAndSet(o, i);
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Common.field2VarHandle.getAndSet(o, i);
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}
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@Test
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@ -390,14 +390,14 @@ class TestZGCEffectiveBarrierElision {
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@IR(counts = { IRNode.Z_GET_AND_SET_P_WITH_BARRIER_FLAG, Common.ELIDED, "1" }, phase = CompilePhase.FINAL_CODE)
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static void testStoreThenAtomic(Outer o, Inner i) {
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o.field1 = i;
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Common.field1VarHandle.getAndSet(o, i);
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Common.field1VarHandle.getAndSet(o, i);
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}
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@Test
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@IR(counts = { IRNode.Z_GET_AND_SET_P_WITH_BARRIER_FLAG, Common.REMAINING, "1" }, phase = CompilePhase.FINAL_CODE)
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@IR(counts = { IRNode.Z_LOAD_P_WITH_BARRIER_FLAG, Common.ELIDED, "1" }, phase = CompilePhase.FINAL_CODE)
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static void testAtomicThenLoad(Outer o, Inner i) {
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Common.field1VarHandle.getAndSet(o, i);
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Common.field1VarHandle.getAndSet(o, i);
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Common.blackhole(o.field1);
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}
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@ -405,7 +405,7 @@ class TestZGCEffectiveBarrierElision {
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@IR(counts = { IRNode.Z_GET_AND_SET_P_WITH_BARRIER_FLAG, Common.REMAINING, "1" }, phase = CompilePhase.FINAL_CODE)
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@IR(counts = { IRNode.Z_STORE_P_WITH_BARRIER_FLAG, Common.ELIDED, "1" }, phase = CompilePhase.FINAL_CODE)
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static void testAtomicThenStore(Outer o, Inner i) {
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Common.field1VarHandle.getAndSet(o, i);
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Common.field1VarHandle.getAndSet(o, i);
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o.field1 = i;
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}
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@ -413,8 +413,8 @@ class TestZGCEffectiveBarrierElision {
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@IR(counts = { IRNode.Z_GET_AND_SET_P_WITH_BARRIER_FLAG, Common.REMAINING, "1" }, phase = CompilePhase.FINAL_CODE)
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@IR(counts = { IRNode.Z_GET_AND_SET_P_WITH_BARRIER_FLAG, Common.ELIDED, "1" }, phase = CompilePhase.FINAL_CODE)
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static void testAtomicThenAtomic(Outer o, Inner i) {
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Common.field1VarHandle.getAndSet(o, i);
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Common.field1VarHandle.getAndSet(o, i);
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Common.field1VarHandle.getAndSet(o, i);
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Common.field1VarHandle.getAndSet(o, i);
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}
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@Test
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@ -100,7 +100,7 @@ import jdk.test.lib.Utils;
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* <p>
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* Unless you have reasons to pick a specific distribution, you are encouraged to rely on {@link #ints()},
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* {@link #longs()}, {@link #doubles()} and {@link #floats()}, which will randomly pick an interesting distribution.
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* This is best practice, because that allows the test to be run under different conditions – maybe only a single
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* This is best practice, because that allows the test to be run under different conditions - maybe only a single
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* distribution can trigger a bug.
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*/
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public final class Generators {
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@ -435,7 +435,7 @@ enum NumberType {
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this.rndFnc = rndFnc;
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}
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public String getСType() {
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public String getCType() {
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return cType;
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}
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@ -443,7 +443,7 @@ enum NumberType {
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return jType;
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}
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public String getСConv() {
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public String getCConv() {
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return cConv;
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}
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@ -792,9 +792,9 @@ class ParameterListGenerator {
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String randomVal = list.get(type).getFnc();
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String ctype = list.get(type).getСType();
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String ctype = list.get(type).getCType();
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String jtype = list.get(type).getJType();
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String cconv = list.get(type).getСConv();
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String cconv = list.get(type).getCConv();
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String jconv = list.get(type).getJConv();
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String varName = "p" + cnt;
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@ -91,7 +91,7 @@ import java.util.Vector;
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* This bug is largely unnoticed because most {@code Raster.create}
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* methods actually create {@link WritableRaster} instances, even
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* when the user did not asked for writable raster. To make this
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* bug apparent, we need to invoke {@code Raster.createRaster(…)}
|
||||
* bug apparent, we need to invoke {@code Raster.createRaster(...)}
|
||||
* with a sample model for which no optimization is provided.
|
||||
*/
|
||||
public class TiledImage implements RenderedImage {
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<xs:schema xmlns:xs="http://www.w3.org/2001/XMLSchema" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" elementFormDefault="unqualified" attributeFormDefault="unqualified" version="1.0">
|
||||
<xs:element name="recording">
|
||||
<xs:complexType>
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user