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8280867: Cpuid1Ecx feature parsing is incorrect for AMD CPUs

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Reviewed-by: kvn, dlong
This commit is contained in:
Aleksey Shipilev 2022-02-01 20:55:39 +00:00
parent fdd9ca74bd
commit a18beb4797
1 changed files with 8 additions and 9 deletions
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17
src/hotspot/cpu/x86/vm_version_x86.hpp
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@ -1,5 +1,5 @@
/*
* Copyright (c) 1997, 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 1997, 2022, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -148,12 +148,11 @@ class VM_Version : public Abstract_VM_Version {
uint32_t LahfSahf : 1,
CmpLegacy : 1,
: 3,
lzcnt_intel : 1,
lzcnt : 1,
sse4a : 1,
misalignsse : 1,
prefetchw : 1,
: 22;
: 23;
} bits;
};
@ -640,10 +639,10 @@ protected:
// Intel features.
if (is_intel()) {
if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0)
if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt != 0) {
result |= CPU_LZCNT;
// for Intel, ecx.bits.misalignsse bit (bit 8) indicates support for prefetchw
if (_cpuid_info.ext_cpuid1_ecx.bits.misalignsse != 0) {
}
if (_cpuid_info.ext_cpuid1_ecx.bits.prefetchw != 0) {
result |= CPU_3DNOW_PREFETCH;
}
if (_cpuid_info.sef_cpuid7_ebx.bits.clwb != 0) {
@ -655,10 +654,10 @@ protected:
// ZX features.
if (is_zx()) {
if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0)
if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt != 0) {
result |= CPU_LZCNT;
// for ZX, ecx.bits.misalignsse bit (bit 8) indicates support for prefetchw
if (_cpuid_info.ext_cpuid1_ecx.bits.misalignsse != 0) {
}
if (_cpuid_info.ext_cpuid1_ecx.bits.prefetchw != 0) {
result |= CPU_3DNOW_PREFETCH;
}
}