8258953: AArch64: move NEON instructions to aarch64_neon.ad
Reviewed-by: njian, aph
This commit is contained in:
Dong Bo
Fei Yang
parent
c5ff454481
commit
aa5bc6edb3
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -57,28 +57,20 @@ dnl
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// ====================VECTOR INSTRUCTIONS==================================
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// ------------------------------ Load/store/reinterpret -----------------------
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// Load vector (16 bits)
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instruct loadV2(vecD dst, memory mem)
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define(`VLoadStore', `
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// ifelse(load, $3, Load, Store) Vector ($6 bits)
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instruct $3V$4`'(vec$5 $7, ifelse($4, 2, memory, vmem$4) mem)
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%{
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predicate(n->as_LoadVector()->memory_size() == 2);
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match(Set dst (LoadVector mem));
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predicate($8`n->as_'ifelse(load, $3, Load, Store)Vector()->memory_size() == $4);
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match(Set ifelse(load, $3, dst (LoadVector mem), mem (StoreVector mem src)));
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ins_cost(4 * INSN_COST);
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format %{ "ldrh $dst,$mem\t# vector (16 bits)" %}
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ins_encode( aarch64_enc_ldrvH(dst, mem) );
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ins_pipe(vload_reg_mem64);
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%}
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// Store Vector (16 bits)
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instruct storeV2(vecD src, memory mem)
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%{
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predicate(n->as_StoreVector()->memory_size() == 2);
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match(Set mem (StoreVector mem src));
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ins_cost(4 * INSN_COST);
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format %{ "strh $mem,$src\t# vector (16 bits)" %}
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ins_encode( aarch64_enc_strvH(src, mem) );
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ins_pipe(vstore_reg_mem64);
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%}
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format %{ "$1 ifelse(load, $3, `$dst,$mem', `$mem,$src')\t# vector ($6 bits)" %}
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ins_encode( `aarch64_enc_'ifelse(load, $3, ldr, str)v$2($7, mem) );
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ins_pipe(v$3`_reg_mem'ifelse(eval($4 * 8), 128, 128, 64));
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%}')dnl
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dnl $1 $2 $3 $4 $5 $6 $7 $8
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VLoadStore(ldrh, H, load, 2, D, 16, dst, )
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VLoadStore(strh, H, store, 2, D, 16, src, )
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dnl
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define(`REINTERPRET', `
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instruct reinterpret$1`'(vec$1 dst)
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@ -1507,3 +1499,795 @@ VFABD(fabd, fabd, 2, F, D, S, 64)
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VFABD(fabd, fabd, 4, F, X, S, 128)
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VFABD(fabd, fabd, 2, D, X, D, 128)
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dnl
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VLoadStore(ldrs, S, load, 4, D, 32, dst, )
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VLoadStore(ldrd, D, load, 8, D, 64, dst, )
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VLoadStore(ldrq, Q, load, 16, X, 128, dst, UseSVE == 0 && )
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VLoadStore(strs, S, store, 4, D, 32, src, )
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VLoadStore(strd, D, store, 8, D, 64, src, )
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VLoadStore(strq, Q, store, 16, X, 128, src, )
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dnl
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define(`VREPLICATE', `
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instruct replicate$3$4$5`'(vec$6 dst, $7 ifelse($7, immI0, zero, $7, immI, con, src))
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%{
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predicate(ifelse($8, UseSVE == 0 && , $8,
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$8, , , $8`
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')n->as_Vector()->length() == $3);
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match(Set dst (Replicate`'ifelse($7, immI0, I, $4) ifelse($7, immI0, zero, $7, immI, con, $7, zero, I, src)));
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ins_cost(INSN_COST);
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format %{ "$1 $dst, $ifelse($7, immI0, zero, $7, immI, con, src)`\t# vector ('ifelse($4$7, SimmI, $3H, $2, eor, 4I, $3$4)`)"' %}
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ins_encode %{
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__ $2(as_FloatRegister($dst$$reg), __ ifelse(
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$2, eor, T16B, T$3`'$9),ifelse(
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`$4 $7', `B immI', ` '$con$$constant & 0xff,
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`$4 $7', `S immI', ` '$con$$constant & 0xffff,
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`$4 $7', `I immI', ` '$con$$constant,
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`$2', eor,`
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as_FloatRegister($dst$$reg),
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as_FloatRegister($dst$$reg)',
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`$7', vRegF,`
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as_FloatRegister($src$$reg)',
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`$7', vRegD,`
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as_FloatRegister($src$$reg)',
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` 'as_Register($src$$reg)));
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%}
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ins_pipe(ifelse($7, immI0, v$1_reg_imm,
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$7, immI, v$1_reg_imm,
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$7, iRegIorL2I, v$1_reg_reg,
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$7, zero, vmovi_reg_imm,
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$7, iRegL, vdup_reg_reg,
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$4, F, vdup_reg_freg, vdup_reg_dreg)`'ifelse($6, X, 128, 64));
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%}')dnl
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dnl $1 $2 $3 $4 $5 $6 $7 $8 $9
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VREPLICATE(dup, dup, 8, B, , D, iRegIorL2I, n->as_Vector()->length() == 4 ||, B)
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VREPLICATE(dup, dup, 16, B, , X, iRegIorL2I, UseSVE == 0 && , B)
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VREPLICATE(movi, mov, 8, B, _imm, D, immI, n->as_Vector()->length() == 4 ||, B)
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VREPLICATE(movi, mov, 16, B, _imm, X, immI, UseSVE == 0 && , B)
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VREPLICATE(dup, dup, 4, S, , D, iRegIorL2I, n->as_Vector()->length() == 2 ||, H)
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VREPLICATE(dup, dup, 8, S, , X, iRegIorL2I, UseSVE == 0 && , H)
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VREPLICATE(movi, mov, 4, S, _imm, D, immI, n->as_Vector()->length() == 2 ||, H)
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VREPLICATE(movi, mov, 8, S, _imm, X, immI, UseSVE == 0 && , H)
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VREPLICATE(dup, dup, 2, I, , D, iRegIorL2I, , S)
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VREPLICATE(dup, dup, 4, I, , X, iRegIorL2I, UseSVE == 0 && , S)
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VREPLICATE(movi, mov, 2, I, _imm, D, immI, , S)
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VREPLICATE(movi, mov, 4, I, _imm, X, immI, UseSVE == 0 && , S)
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VREPLICATE(dup, dup, 2, L, , X, iRegL, UseSVE == 0 && , D)
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VREPLICATE(movi, eor, 2, L, _zero, X, immI0, UseSVE == 0 && , D)
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VREPLICATE(dup, dup, 2, F, , D, vRegF, , S)
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VREPLICATE(dup, dup, 4, F, , X, vRegF, UseSVE == 0 && , S)
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VREPLICATE(dup, dup, 2, D, , X, vRegD, UseSVE == 0 && , D)
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dnl
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// ====================REDUCTION ARITHMETIC====================================
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dnl
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define(`REDUCE_ADD_INT', `
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instruct reduce_add$1$2`'(iRegINoSp dst, iRegIorL2I isrc, vec$3 vsrc, ifelse($1, 2, iRegINoSp tmp, vecX vtmp), iRegINoSp ifelse($1, 2, tmp2, itmp))
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%{
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predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_INT);
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match(Set dst (AddReductionVI isrc vsrc));
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ins_cost(INSN_COST);
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effect(TEMP ifelse($1, 2, tmp, vtmp), TEMP ifelse($1, 2, tmp2, itmp));
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format %{ ifelse($1, 2, `"umov $tmp, $vsrc, S, 0\n\t"
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"umov $tmp2, $vsrc, S, 1\n\t"
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"addw $tmp, $isrc, $tmp\n\t"
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"addw $dst, $tmp, $tmp2\t# add reduction2I"',`"addv $vtmp, T4S, $vsrc\n\t"
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"umov $itmp, $vtmp, S, 0\n\t"
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"addw $dst, $itmp, $isrc\t# add reduction4I"')
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%}
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ins_encode %{
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ifelse($1, 2, `__ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ S, 0);
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__ umov($tmp2$$Register, as_FloatRegister($vsrc$$reg), __ S, 1);
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__ addw($tmp$$Register, $isrc$$Register, $tmp$$Register);
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__ addw($dst$$Register, $tmp$$Register, $tmp2$$Register);', `__ addv(as_FloatRegister($vtmp$$reg), __ T4S,
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as_FloatRegister($vsrc$$reg));
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__ umov($itmp$$Register, as_FloatRegister($vtmp$$reg), __ S, 0);
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__ addw($dst$$Register, $itmp$$Register, $isrc$$Register);')
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%}
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ins_pipe(pipe_class_default);
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%}')dnl
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dnl $1 $2 $3
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REDUCE_ADD_INT(2, I, D)
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REDUCE_ADD_INT(4, I, X)
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dnl
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define(`REDUCE_MUL_INT', `
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instruct reduce_mul$1$2`'(iRegINoSp dst, iRegIorL2I isrc, vec$3 vsrc, ifelse($1, 2, iRegINoSp tmp`)', vecX vtmp`,' iRegINoSp itmp`)')
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%{
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predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_INT);
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match(Set dst (MulReductionVI isrc vsrc));
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ins_cost(INSN_COST);
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effect(TEMP ifelse($1, 2, tmp, vtmp), TEMP ifelse($1, 2, dst, itmp`,' TEMP dst));
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format %{ ifelse($1, 2, `"umov $tmp, $vsrc, S, 0\n\t"
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"mul $dst, $tmp, $isrc\n\t"
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"umov $tmp, $vsrc, S, 1\n\t"
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"mul $dst, $tmp, $dst\t# mul reduction2I"',`"ins $vtmp, D, $vsrc, 0, 1\n\t"
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"mulv $vtmp, T2S, $vtmp, $vsrc\n\t"
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"umov $itmp, $vtmp, S, 0\n\t"
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"mul $dst, $itmp, $isrc\n\t"
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"umov $itmp, $vtmp, S, 1\n\t"
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"mul $dst, $itmp, $dst\t# mul reduction4I"')
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%}
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ins_encode %{
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ifelse($1, 2, `__ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ S, 0);
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__ mul($dst$$Register, $tmp$$Register, $isrc$$Register);
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__ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ S, 1);
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__ mul($dst$$Register, $tmp$$Register, $dst$$Register);', `__ ins(as_FloatRegister($vtmp$$reg), __ D,
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as_FloatRegister($vsrc$$reg), 0, 1);
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__ mulv(as_FloatRegister($vtmp$$reg), __ T2S,
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as_FloatRegister($vtmp$$reg), as_FloatRegister($vsrc$$reg));
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__ umov($itmp$$Register, as_FloatRegister($vtmp$$reg), __ S, 0);
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__ mul($dst$$Register, $itmp$$Register, $isrc$$Register);
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__ umov($itmp$$Register, as_FloatRegister($vtmp$$reg), __ S, 1);
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__ mul($dst$$Register, $itmp$$Register, $dst$$Register);')
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%}
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ins_pipe(pipe_class_default);
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%}')dnl
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dnl $1 $2 $3
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REDUCE_MUL_INT(2, I, D)
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REDUCE_MUL_INT(4, I, X)
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dnl
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define(`REDUCE_MULORADD_FORD', `
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instruct reduce_$6$2$3`'(vReg$3 dst, vReg$3 $4src, vec$5 vsrc, vec$5 tmp)
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%{
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match(Set dst (ifelse($6, add, Add, Mul)ReductionV$3 $4src vsrc));
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ins_cost(INSN_COST);
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effect(TEMP tmp, TEMP dst);
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format %{ "$1 $dst, $$4src, $vsrc\n\t"
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"ins $tmp, ifelse($3, F, S, D), $vsrc, 0, 1\n\t"
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ifelse($2, 2, `"$1 $dst, $dst, $tmp\t# $6 reduction$2$3"',
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`"$1 $dst, $dst, $tmp\n\t"
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"ins $tmp, S, $vsrc, 0, 2\n\t"
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"$1 $dst, $dst, $tmp\n\t"
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"ins $tmp, S, $vsrc, 0, 3\n\t"
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"$1 $dst, $dst, $tmp\t# $6 reduction4F"')
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%}
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ins_encode %{
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__ $1(as_FloatRegister($dst$$reg),
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as_FloatRegister($$4src$$reg), as_FloatRegister($vsrc$$reg));
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__ ins(as_FloatRegister($tmp$$reg), __ ifelse($3, F, S, D),
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as_FloatRegister($vsrc$$reg), 0, 1);
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__ $1(as_FloatRegister($dst$$reg),
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as_FloatRegister($dst$$reg), as_FloatRegister($tmp$$reg));ifelse($2, 4, `
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__ ins(as_FloatRegister($tmp$$reg), __ ifelse($3, F, S, D),
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as_FloatRegister($vsrc$$reg), 0, 2);
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__ $1(as_FloatRegister($dst$$reg),
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as_FloatRegister($dst$$reg), as_FloatRegister($tmp$$reg));
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__ ins(as_FloatRegister($tmp$$reg), __ S,
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as_FloatRegister($vsrc$$reg), 0, 3);
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__ $1(as_FloatRegister($dst$$reg),
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as_FloatRegister($dst$$reg), as_FloatRegister($tmp$$reg));')
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%}
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ins_pipe(pipe_class_default);
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%}')dnl
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dnl $1 $2 $3 $4 $5 $6
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REDUCE_MULORADD_FORD(fadds, 2, F, f, D, add)
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REDUCE_MULORADD_FORD(fadds, 4, F, f, X, add)
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REDUCE_MULORADD_FORD(fmuls, 2, F, f, D, mul)
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REDUCE_MULORADD_FORD(fmuls, 4, F, f, X, mul)
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REDUCE_MULORADD_FORD(faddd, 2, D, d, X, add)
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REDUCE_MULORADD_FORD(fmuld, 2, D, d, X, mul)
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// ====================VECTOR ARITHMETIC=======================================
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// --------------------------------- ADD --------------------------------------
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define(`VADD', `
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instruct vadd$2$3`'(vec$4 dst, vec$4 src1, vec$4 src2)
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%{ifelse($2$3, 8B, `
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predicate(n->as_Vector()->length() == 4 ||
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n->as_Vector()->length() == 8);',
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$2$3, 4S, `
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predicate(n->as_Vector()->length() == 2 ||
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n->as_Vector()->length() == 4);',
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$2$5, 2D, , `
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predicate(n->as_Vector()->length() == $2);')
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match(Set dst (AddV$3 src1 src2));
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ins_cost(INSN_COST);
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format %{ "$1 $dst,$src1,$src2\t# vector ($2$5)" %}
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ins_encode %{
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__ $1(as_FloatRegister($dst$$reg), __ T$2`'ifelse($5, L, D, $5),
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as_FloatRegister($src1$$reg),
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as_FloatRegister($src2$$reg));
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%}
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ins_pipe(vdop`'ifelse($3, F, _fp, $3, D, _fp)`'ifelse($4, D, 64, 128));
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%}')dnl
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dnl $1 $2 $3 $4 $5
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VADD(addv, 8, B, D, B)
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VADD(addv, 16, B, X, B)
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VADD(addv, 4, S, D, H)
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VADD(addv, 8, S, X, H)
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VADD(addv, 2, I, D, S)
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VADD(addv, 4, I, X, S)
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VADD(addv, 2, L, X, L)
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VADD(fadd, 2, F, D, S)
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VADD(fadd, 4, F, X, S)
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VADD(fadd, 2, D, X, D)
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// --------------------------------- SUB --------------------------------------
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define(`VSUB', `
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instruct vsub$2$3`'(vec$4 dst, vec$4 src1, vec$4 src2)
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%{ifelse($2$3, 8B, `
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predicate(n->as_Vector()->length() == 4 ||
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n->as_Vector()->length() == 8);',
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$2$3, 4S, `
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predicate(n->as_Vector()->length() == 2 ||
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n->as_Vector()->length() == 4);',`
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predicate(n->as_Vector()->length() == $2);')
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match(Set dst (SubV$3 src1 src2));
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ins_cost(INSN_COST);
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format %{ "$1 $dst,$src1,$src2\t# vector ($2$5)" %}
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ins_encode %{
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__ $1(as_FloatRegister($dst$$reg), __ T$2`'ifelse($5, L, D, $5),
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as_FloatRegister($src1$$reg),
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as_FloatRegister($src2$$reg));
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%}
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ins_pipe(vdop`'ifelse($3, F, _fp, $3, D, _fp)`'ifelse($4, D, 64, 128));
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%}')dnl
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dnl $1 $2 $3 $4 $5
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VSUB(subv, 8, B, D, B)
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VSUB(subv, 16, B, X, B)
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VSUB(subv, 4, S, D, H)
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VSUB(subv, 8, S, X, H)
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VSUB(subv, 2, I, D, S)
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VSUB(subv, 4, I, X, S)
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VSUB(subv, 2, L, X, L)
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VSUB(fsub, 2, F, D, S)
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VSUB(fsub, 4, F, X, S)
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VSUB(fsub, 2, D, X, D)
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// --------------------------------- MUL --------------------------------------
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define(`VMUL', `
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instruct vmul$2$3`'(vec$4 dst, vec$4 src1, vec$4 src2)
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%{ifelse($2$3, 8B, `
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predicate(n->as_Vector()->length() == 4 ||
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n->as_Vector()->length() == 8);',
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$2$3, 4S, `
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predicate(n->as_Vector()->length() == 2 ||
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n->as_Vector()->length() == 4);',`
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predicate(n->as_Vector()->length() == $2);')
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match(Set dst (MulV$3 src1 src2));
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ins_cost(INSN_COST);
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format %{ "$1 $dst,$src1,$src2\t# vector ($2$5)" %}
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ins_encode %{
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__ $1(as_FloatRegister($dst$$reg), __ T$2`'ifelse($5, L, D, $5),
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as_FloatRegister($src1$$reg),
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as_FloatRegister($src2$$reg));
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%}
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ins_pipe(vmul`'ifelse($3, F, div_fp, $3, D, div_fp)`'ifelse($4, D, 64, 128));
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%}')dnl
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dnl $1 $2 $3 $4 $5
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VMUL(mulv, 8, B, D, B)
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VMUL(mulv, 16, B, X, B)
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VMUL(mulv, 4, S, D, H)
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VMUL(mulv, 8, S, X, H)
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VMUL(mulv, 2, I, D, S)
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VMUL(mulv, 4, I, X, S)
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VMUL(fmul, 2, F, D, S)
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VMUL(fmul, 4, F, X, S)
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VMUL(fmul, 2, D, X, D)
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// --------------------------------- MLA --------------------------------------
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define(`VMLA', `ifelse($1, fmla, `
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// dst + src1 * src2')
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instruct vmla$2$3`'(vec$4 dst, vec$4 src1, vec$4 src2)
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%{ifelse($2$3, 4S, `
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predicate(n->as_Vector()->length() == 2 ||
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n->as_Vector()->length() == 4);', $1, fmla, `
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predicate(UseFMA && n->as_Vector()->length() == $2);', `
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predicate(n->as_Vector()->length() == $2);')
|
||||
match(Set dst (ifelse($1, mlav, `AddV'$3` dst (MulV$3 src1 src2)', FmaV$3 `dst (Binary src1 src2)')));
|
||||
ins_cost(INSN_COST);
|
||||
format %{ "$1 $dst,$src1,$src2\t# vector ($2$5)" %}
|
||||
ins_encode %{
|
||||
__ $1(as_FloatRegister($dst$$reg), __ T$2`'ifelse($5, L, D, $5),
|
||||
as_FloatRegister($src1$$reg),
|
||||
as_FloatRegister($src2$$reg));
|
||||
%}
|
||||
ins_pipe(vm`'ifelse($3, F, uldiv_fp, $3, D, uldiv_fp, la)`'ifelse($4, D, 64, 128));
|
||||
%}')dnl
|
||||
dnl $1 $2 $3 $4 $5
|
||||
VMLA(mlav, 4, S, D, H)
|
||||
VMLA(mlav, 8, S, X, H)
|
||||
VMLA(mlav, 2, I, D, S)
|
||||
VMLA(mlav, 4, I, X, S)
|
||||
VMLA(fmla, 2, F, D, S)
|
||||
VMLA(fmla, 4, F, X, S)
|
||||
VMLA(fmla, 2, D, X, D)
|
||||
|
||||
// --------------------------------- MLS --------------------------------------
|
||||
define(`VMLS', `ifelse($1, fmls, `
|
||||
// dst - src1 * src2')
|
||||
instruct vmls$2$3`'(vec$4 dst, vec$4 src1, vec$4 src2) %{ifelse($2$3, 4S, `
|
||||
predicate(n->as_Vector()->length() == 2 ||
|
||||
n->as_Vector()->length() == 4);', $1, fmls, `
|
||||
predicate(UseFMA && n->as_Vector()->length() == $2);', `
|
||||
predicate(n->as_Vector()->length() == $2);')
|
||||
match(Set dst (ifelse($1, mlsv, `SubV'$3` dst (MulV$3 src1 src2)', FmaV$3 `dst (Binary (NegV'$3 `src1) src2)));
|
||||
match(Set dst (FmaV$3 dst (Binary src1 (NegV'$3 `src2))')));
|
||||
ins_cost(INSN_COST);
|
||||
format %{ "$1 $dst,$src1,$src2\t# vector ($2$5)" %}
|
||||
ins_encode %{
|
||||
__ $1(as_FloatRegister($dst$$reg), __ T$2`'ifelse($5, L, D, $5),
|
||||
as_FloatRegister($src1$$reg),
|
||||
as_FloatRegister($src2$$reg));
|
||||
%}
|
||||
ins_pipe(vm`'ifelse($3, F, uldiv_fp, $3, D, uldiv_fp, la)`'ifelse($4, D, 64, 128));
|
||||
%}')dnl
|
||||
dnl $1 $2 $3 $4 $5
|
||||
VMLS(mlsv, 4, S, D, H)
|
||||
VMLS(mlsv, 8, S, X, H)
|
||||
VMLS(mlsv, 2, I, D, S)
|
||||
VMLS(mlsv, 4, I, X, S)
|
||||
VMLS(fmls, 2, F, D, S)
|
||||
VMLS(fmls, 4, F, X, S)
|
||||
VMLS(fmls, 2, D, X, D)
|
||||
|
||||
// --------------- Vector Multiply-Add Shorts into Integer --------------------
|
||||
|
||||
instruct vmuladdS2I(vecX dst, vecX src1, vecX src2, vecX tmp) %{
|
||||
predicate(n->in(1)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
|
||||
match(Set dst (MulAddVS2VI src1 src2));
|
||||
ins_cost(INSN_COST);
|
||||
effect(TEMP_DEF dst, TEMP tmp);
|
||||
format %{ "smullv $tmp, $src1, $src2\t# vector (4H)\n\t"
|
||||
"smullv $dst, $src1, $src2\t# vector (8H)\n\t"
|
||||
"addpv $dst, $tmp, $dst\t# vector (4S)\n\t" %}
|
||||
ins_encode %{
|
||||
__ smullv(as_FloatRegister($tmp$$reg), __ T4H,
|
||||
as_FloatRegister($src1$$reg),
|
||||
as_FloatRegister($src2$$reg));
|
||||
__ smullv(as_FloatRegister($dst$$reg), __ T8H,
|
||||
as_FloatRegister($src1$$reg),
|
||||
as_FloatRegister($src2$$reg));
|
||||
__ addpv(as_FloatRegister($dst$$reg), __ T4S,
|
||||
as_FloatRegister($tmp$$reg),
|
||||
as_FloatRegister($dst$$reg));
|
||||
%}
|
||||
ins_pipe(vmuldiv_fp128);
|
||||
%}
|
||||
|
||||
// --------------------------------- DIV --------------------------------------
|
||||
define(`VDIV', `
|
||||
instruct vdiv$2$3`'(vec$4 dst, vec$4 src1, vec$4 src2)
|
||||
%{
|
||||
predicate(n->as_Vector()->length() == $2);
|
||||
match(Set dst (DivV$3 src1 src2));
|
||||
ins_cost(INSN_COST);
|
||||
format %{ "$1 $dst,$src1,$src2\t# vector ($2$5)" %}
|
||||
ins_encode %{
|
||||
__ $1(as_FloatRegister($dst$$reg), __ T$2`'ifelse($5, L, D, $5),
|
||||
as_FloatRegister($src1$$reg),
|
||||
as_FloatRegister($src2$$reg));
|
||||
%}
|
||||
ins_pipe(vmuldiv_fp`'ifelse($4, D, 64, 128));
|
||||
%}')dnl
|
||||
dnl $1 $2 $3 $4 $5
|
||||
VDIV(fdiv, 2, F, D, S)
|
||||
VDIV(fdiv, 4, F, X, S)
|
||||
VDIV(fdiv, 2, D, X, D)
|
||||
|
||||
// --------------------------------- SQRT -------------------------------------
|
||||
define(`VSQRT', `
|
||||
instruct vsqrt$2$3`'(vec$4 dst, vec$4 src)
|
||||
%{
|
||||
predicate(n->as_Vector()->length() == $2);
|
||||
match(Set dst (SqrtV$3 src));
|
||||
format %{ "$1 $dst, $src\t# vector ($2$3)" %}
|
||||
ins_encode %{
|
||||
__ $1(as_FloatRegister($dst$$reg), __ T$2$5, as_FloatRegister($src$$reg));
|
||||
%}
|
||||
ins_pipe(v`'ifelse($2$3, 2F, unop, sqrt)_fp`'ifelse($4, D, 64, 128));
|
||||
%}')dnl
|
||||
dnl $1 $2 $3 $4 $5
|
||||
VSQRT(fsqrt, 2, F, D, S)
|
||||
VSQRT(fsqrt, 4, F, X, S)
|
||||
VSQRT(fsqrt, 2, D, X, D)
|
||||
|
||||
// --------------------------------- NEG --------------------------------------
|
||||
define(`VNEG', `
|
||||
instruct vneg$2$3`'(vec$4 dst, vec$4 src)
|
||||
%{
|
||||
predicate(n->as_Vector()->length() == $2);
|
||||
match(Set dst (NegV$3 src));
|
||||
ins_cost(INSN_COST * 3);
|
||||
format %{ "$1 $dst,$src\t# vector ($2$5)" %}
|
||||
ins_encode %{
|
||||
__ $1(as_FloatRegister($dst$$reg), __ T$2`'ifelse($5, L, D, $5),
|
||||
as_FloatRegister($src$$reg));
|
||||
%}
|
||||
ins_pipe(vunop_fp`'ifelse($4, D, 64, 128));
|
||||
%}')dnl
|
||||
dnl $1 $2 $3 $4 $5
|
||||
VNEG(fneg, 2, F, D, S)
|
||||
VNEG(fneg, 4, F, X, S)
|
||||
VNEG(fneg, 2, D, X, D)
|
||||
dnl
|
||||
define(`VLOGICAL', `
|
||||
instruct v$3$5$6`'(vec$7 dst, vec$7 src1, vec$7 src2)
|
||||
%{
|
||||
predicate(ifelse($5, 8, n->as_Vector()->length_in_bytes() == 4 ||`
|
||||
')n->as_Vector()->length_in_bytes() == $5);
|
||||
match(Set dst ($4V src1 src2));
|
||||
ins_cost(INSN_COST);
|
||||
format %{ "$1 $dst,$src1,$src2\t# vector ($5$6)" %}
|
||||
ins_encode %{
|
||||
__ $2(as_FloatRegister($dst$$reg), __ T$5$6,
|
||||
as_FloatRegister($src1$$reg),
|
||||
as_FloatRegister($src2$$reg));
|
||||
%}
|
||||
ins_pipe(vlogical`'ifelse($7, D, 64, 128));
|
||||
%}')dnl
|
||||
|
||||
// --------------------------------- AND --------------------------------------
|
||||
dnl $1 $2 $3 $4 $5 $6 $7
|
||||
VLOGICAL(and, andr, and, And, 8, B, D)
|
||||
VLOGICAL(and, andr, and, And, 16, B, X)
|
||||
|
||||
// --------------------------------- OR ---------------------------------------
|
||||
VLOGICAL(orr, orr, or, Or, 8, B, D)
|
||||
VLOGICAL(orr, orr, or, Or, 16, B, X)
|
||||
|
||||
// --------------------------------- XOR --------------------------------------
|
||||
VLOGICAL(xor, eor, xor, Xor, 8, B, D)
|
||||
VLOGICAL(xor, eor, xor, Xor, 16, B, X)
|
||||
|
||||
// ------------------------------ Shift ---------------------------------------
|
||||
dnl
|
||||
define(`VSHIFTCNT', `
|
||||
instruct vshiftcnt$3$4`'(vec$5 dst, iRegIorL2I cnt) %{
|
||||
predicate(ifelse($3, 8, n->as_Vector()->length_in_bytes() == 4 ||`
|
||||
')n->as_Vector()->length_in_bytes() == $3);
|
||||
match(Set dst (LShiftCntV cnt));
|
||||
match(Set dst (RShiftCntV cnt));
|
||||
format %{ "$1 $dst, $cnt\t# shift count vector ($3$4)" %}
|
||||
ins_encode %{
|
||||
__ $2(as_FloatRegister($dst$$reg), __ T$3$4, as_Register($cnt$$reg));
|
||||
%}
|
||||
ins_pipe(vdup_reg_reg`'ifelse($5, D, 64, 128));
|
||||
%}')dnl
|
||||
dnl $1 $2 $3 $4 $5
|
||||
VSHIFTCNT(dup, dup, 8, B, D)
|
||||
VSHIFTCNT(dup, dup, 16, B, X)
|
||||
dnl
|
||||
define(`VSLL', `
|
||||
instruct vsll$3$4`'(vec$6 dst, vec$6 src, vec$6 shift) %{
|
||||
predicate(ifelse($3$4, 8B, n->as_Vector()->length() == 4 ||`
|
||||
',
|
||||
$3$4, 4S, n->as_Vector()->length() == 2 ||`
|
||||
')n->as_Vector()->length() == $3);
|
||||
match(Set dst (LShiftV$4 src shift));
|
||||
ins_cost(INSN_COST);
|
||||
format %{ "$1 $dst,$src,$shift\t# vector ($3$5)" %}
|
||||
ins_encode %{
|
||||
__ $2(as_FloatRegister($dst$$reg), __ T$3$5,
|
||||
as_FloatRegister($src$$reg),
|
||||
as_FloatRegister($shift$$reg));
|
||||
%}
|
||||
ins_pipe(vshift`'ifelse($6, D, 64, 128));
|
||||
%}')dnl
|
||||
dnl
|
||||
define(`VSRA', `
|
||||
instruct vsra$3$4`'(vec$6 dst, vec$6 src, vec$6 shift, vec$6 tmp) %{
|
||||
predicate(ifelse($3$4, 8B, n->as_Vector()->length() == 4 ||`
|
||||
',
|
||||
$3$4, 4S, n->as_Vector()->length() == 2 ||`
|
||||
')n->as_Vector()->length() == $3);
|
||||
match(Set dst (RShiftV$4 src shift));
|
||||
ins_cost(INSN_COST);
|
||||
effect(TEMP tmp);
|
||||
format %{ "$1 $tmp,$shift\t"
|
||||
"$2 $dst,$src,$tmp\t# vector ($3$5)" %}
|
||||
ins_encode %{
|
||||
__ $1(as_FloatRegister($tmp$$reg), __ T`'ifelse($6, D, 8B, 16B),
|
||||
as_FloatRegister($shift$$reg));
|
||||
__ $2(as_FloatRegister($dst$$reg), __ T$3$5,
|
||||
as_FloatRegister($src$$reg),
|
||||
as_FloatRegister($tmp$$reg));
|
||||
%}
|
||||
ins_pipe(vshift`'ifelse($6, D, 64, 128));
|
||||
%}')dnl
|
||||
dnl
|
||||
define(`VSRL', `
|
||||
instruct vsrl$3$4`'(vec$6 dst, vec$6 src, vec$6 shift, vec$6 tmp) %{
|
||||
predicate(ifelse($3$4, 8B, n->as_Vector()->length() == 4 ||`
|
||||
',
|
||||
$3$4, 4S, n->as_Vector()->length() == 2 ||`
|
||||
')n->as_Vector()->length() == $3);
|
||||
match(Set dst (URShiftV$4 src shift));
|
||||
ins_cost(INSN_COST);
|
||||
effect(TEMP tmp);
|
||||
format %{ "$1 $tmp,$shift\t"
|
||||
"$2 $dst,$src,$tmp\t# vector ($3$5)" %}
|
||||
ins_encode %{
|
||||
__ $1(as_FloatRegister($tmp$$reg), __ T`'ifelse($6, D, 8B, 16B),
|
||||
as_FloatRegister($shift$$reg));
|
||||
__ $2(as_FloatRegister($dst$$reg), __ T$3$5,
|
||||
as_FloatRegister($src$$reg),
|
||||
as_FloatRegister($tmp$$reg));
|
||||
%}
|
||||
ins_pipe(vshift`'ifelse($6, D, 64, 128));
|
||||
%}')dnl
|
||||
dnl
|
||||
define(`VSLL_IMM', `
|
||||
instruct vsll$3$4_imm`'(vec$6 dst, vec$6 src, immI shift) %{
|
||||
predicate(ifelse($3$4, 8B, n->as_Vector()->length() == 4 ||`
|
||||
',
|
||||
$3$4, 4S, n->as_Vector()->length() == 2 ||`
|
||||
')n->as_Vector()->length() == $3);
|
||||
match(Set dst (LShiftV$4 src (LShiftCntV shift)));
|
||||
ins_cost(INSN_COST);
|
||||
format %{ "$1 $dst, $src, $shift\t# vector ($3$5)" %}
|
||||
ins_encode %{ifelse($4, B,`
|
||||
int sh = (int)$shift$$constant;
|
||||
if (sh >= 8) {
|
||||
__ eor(as_FloatRegister($dst$$reg), __ ifelse($6, D, T8B, T16B),
|
||||
as_FloatRegister($src$$reg),
|
||||
as_FloatRegister($src$$reg));
|
||||
} else {
|
||||
__ $2(as_FloatRegister($dst$$reg), __ T$3$5,
|
||||
as_FloatRegister($src$$reg), sh);
|
||||
}', $4, S,`
|
||||
int sh = (int)$shift$$constant;
|
||||
if (sh >= 16) {
|
||||
__ eor(as_FloatRegister($dst$$reg), __ ifelse($6, D, T8B, T16B),
|
||||
as_FloatRegister($src$$reg),
|
||||
as_FloatRegister($src$$reg));
|
||||
} else {
|
||||
__ $2(as_FloatRegister($dst$$reg), __ T$3$5,
|
||||
as_FloatRegister($src$$reg), sh);
|
||||
}', `
|
||||
__ $2(as_FloatRegister($dst$$reg), __ T$3$5,
|
||||
as_FloatRegister($src$$reg),
|
||||
(int)$shift$$constant);')
|
||||
%}
|
||||
ins_pipe(vshift`'ifelse($6, D, 64, 128)_imm);
|
||||
%}')dnl
|
||||
define(`VSRA_IMM', `
|
||||
instruct vsra$3$4_imm`'(vec$6 dst, vec$6 src, immI shift) %{
|
||||
predicate(ifelse($3$4, 8B, n->as_Vector()->length() == 4 ||`
|
||||
',
|
||||
$3$4, 4S, n->as_Vector()->length() == 2 ||`
|
||||
')n->as_Vector()->length() == $3);
|
||||
match(Set dst (RShiftV$4 src (RShiftCntV shift)));
|
||||
ins_cost(INSN_COST);
|
||||
format %{ "$1 $dst, $src, $shift\t# vector ($3$5)" %}
|
||||
ins_encode %{ifelse($4, B,`
|
||||
int sh = (int)$shift$$constant;
|
||||
if (sh >= 8) sh = 7;
|
||||
__ $2(as_FloatRegister($dst$$reg), __ T$3$5,
|
||||
as_FloatRegister($src$$reg), sh);', $4, S,`
|
||||
int sh = (int)$shift$$constant;
|
||||
if (sh >= 16) sh = 15;
|
||||
__ $2(as_FloatRegister($dst$$reg), __ T$3$5,
|
||||
as_FloatRegister($src$$reg), sh);', `
|
||||
__ $2(as_FloatRegister($dst$$reg), __ T$3$5,
|
||||
as_FloatRegister($src$$reg),
|
||||
(int)$shift$$constant);')
|
||||
%}
|
||||
ins_pipe(vshift`'ifelse($6, D, 64, 128)_imm);
|
||||
%}')dnl
|
||||
dnl
|
||||
define(`VSRL_IMM', `
|
||||
instruct vsrl$3$4_imm`'(vec$6 dst, vec$6 src, immI shift) %{
|
||||
predicate(ifelse($3$4, 8B, n->as_Vector()->length() == 4 ||`
|
||||
',
|
||||
$3$4, 4S, n->as_Vector()->length() == 2 ||`
|
||||
')n->as_Vector()->length() == $3);
|
||||
match(Set dst (URShiftV$4 src (RShiftCntV shift)));
|
||||
ins_cost(INSN_COST);
|
||||
format %{ "$1 $dst, $src, $shift\t# vector ($3$5)" %}
|
||||
ins_encode %{ifelse($4, B,`
|
||||
int sh = (int)$shift$$constant;
|
||||
if (sh >= 8) {
|
||||
__ eor(as_FloatRegister($dst$$reg), __ ifelse($6, D, T8B, T16B),
|
||||
as_FloatRegister($src$$reg),
|
||||
as_FloatRegister($src$$reg));
|
||||
} else {
|
||||
__ $2(as_FloatRegister($dst$$reg), __ T$3$5,
|
||||
as_FloatRegister($src$$reg), sh);
|
||||
}', $4, S,`
|
||||
int sh = (int)$shift$$constant;
|
||||
if (sh >= 16) {
|
||||
__ eor(as_FloatRegister($dst$$reg), __ ifelse($6, D, T8B, T16B),
|
||||
as_FloatRegister($src$$reg),
|
||||
as_FloatRegister($src$$reg));
|
||||
} else {
|
||||
__ $2(as_FloatRegister($dst$$reg), __ T$3$5,
|
||||
as_FloatRegister($src$$reg), sh);
|
||||
}', `
|
||||
__ $2(as_FloatRegister($dst$$reg), __ T$3$5,
|
||||
as_FloatRegister($src$$reg),
|
||||
(int)$shift$$constant);')
|
||||
%}
|
||||
ins_pipe(vshift`'ifelse($6, D, 64, 128)_imm);
|
||||
%}')dnl
|
||||
dnl
|
||||
define(`VSRLA_IMM', `
|
||||
instruct vsrla$3$4_imm`'(vec$6 dst, vec$6 src, immI shift) %{
|
||||
predicate(n->as_Vector()->length() == $3);
|
||||
match(Set dst (AddV$4 dst (URShiftV$4 src (RShiftCntV shift))));
|
||||
ins_cost(INSN_COST);
|
||||
format %{ "$1 $dst, $src, $shift\t# vector ($3$5)" %}
|
||||
ins_encode %{ifelse($4, B,`
|
||||
int sh = (int)$shift$$constant;
|
||||
if (sh < 8) {
|
||||
__ $2(as_FloatRegister($dst$$reg), __ T$3$5,
|
||||
as_FloatRegister($src$$reg), sh);
|
||||
}', $4, S,`
|
||||
int sh = (int)$shift$$constant;
|
||||
if (sh < 16) {
|
||||
__ $2(as_FloatRegister($dst$$reg), __ T$3$5,
|
||||
as_FloatRegister($src$$reg), sh);
|
||||
}', `
|
||||
__ $2(as_FloatRegister($dst$$reg), __ T$3$5,
|
||||
as_FloatRegister($src$$reg),
|
||||
(int)$shift$$constant);')
|
||||
%}
|
||||
ins_pipe(vshift`'ifelse($6, D, 64, 128)_imm);
|
||||
%}')dnl
|
||||
dnl
|
||||
define(`VSRAA_IMM', `
|
||||
instruct vsraa$3$4_imm`'(vec$6 dst, vec$6 src, immI shift) %{
|
||||
predicate(n->as_Vector()->length() == $3);
|
||||
match(Set dst (AddV$4 dst (RShiftV$4 src (RShiftCntV shift))));
|
||||
ins_cost(INSN_COST);
|
||||
format %{ "$1 $dst, $src, $shift\t# vector ($3$5)" %}
|
||||
ins_encode %{ifelse($4, B,`
|
||||
int sh = (int)$shift$$constant;
|
||||
if (sh >= 8) sh = 7;
|
||||
__ $2(as_FloatRegister($dst$$reg), __ T$3$5,
|
||||
as_FloatRegister($src$$reg), sh);', $4, S,`
|
||||
int sh = (int)$shift$$constant;
|
||||
if (sh >= 16) sh = 15;
|
||||
__ $2(as_FloatRegister($dst$$reg), __ T$3$5,
|
||||
as_FloatRegister($src$$reg), sh);', `
|
||||
__ $2(as_FloatRegister($dst$$reg), __ T$3$5,
|
||||
as_FloatRegister($src$$reg),
|
||||
(int)$shift$$constant);')
|
||||
%}
|
||||
ins_pipe(vshift`'ifelse($6, D, 64, 128)_imm);
|
||||
%}')dnl
|
||||
dnl $1 $2 $3 $4 $5 $6
|
||||
VSLL(sshl, sshl, 8, B, B, D)
|
||||
VSLL(sshl, sshl, 16, B, B, X)
|
||||
|
||||
// Right shifts with vector shift count on aarch64 SIMD are implemented
|
||||
// as left shift by negative shift count.
|
||||
// There are two cases for vector shift count.
|
||||
//
|
||||
// Case 1: The vector shift count is from replication.
|
||||
// | |
|
||||
// LoadVector RShiftCntV
|
||||
// | /
|
||||
// RShiftVI
|
||||
// Note: In inner loop, multiple neg instructions are used, which can be
|
||||
// moved to outer loop and merge into one neg instruction.
|
||||
//
|
||||
// Case 2: The vector shift count is from loading.
|
||||
// This case isn't supported by middle-end now. But it's supported by
|
||||
// panama/vectorIntrinsics(JEP 338: Vector API).
|
||||
// | |
|
||||
// LoadVector LoadVector
|
||||
// | /
|
||||
// RShiftVI
|
||||
//
|
||||
dnl $1 $2 $3 $4 $5 $6
|
||||
VSRA(negr, sshl, 8, B, B, D)
|
||||
VSRA(negr, sshl, 16, B, B, X)
|
||||
VSRL(negr, ushl, 8, B, B, D)
|
||||
VSRL(negr, ushl, 16, B, B, X)
|
||||
VSLL_IMM(shl, shl, 8, B, B, D)
|
||||
VSLL_IMM(shl, shl, 16, B, B, X)
|
||||
VSRA_IMM(sshr, sshr, 8, B, B, D)
|
||||
VSRA_IMM(sshr, sshr, 16, B, B, X)
|
||||
VSRL_IMM(ushr, ushr, 8, B, B, D)
|
||||
VSRL_IMM(ushr, ushr, 16, B, B, X)
|
||||
VSLL(sshl, sshl, 4, S, H, D)
|
||||
VSLL(sshl, sshl, 8, S, H, X)
|
||||
VSRA(negr, sshl, 4, S, H, D)
|
||||
VSRA(negr, sshl, 8, S, H, X)
|
||||
VSRL(negr, ushl, 4, S, H, D)
|
||||
VSRL(negr, ushl, 8, S, H, X)
|
||||
VSLL_IMM(shl, shl, 4, S, H, D)
|
||||
VSLL_IMM(shl, shl, 8, S, H, X)
|
||||
VSRA_IMM(sshr, sshr, 4, S, H, D)
|
||||
VSRA_IMM(sshr, sshr, 8, S, H, X)
|
||||
VSRL_IMM(ushr, ushr, 4, S, H, D)
|
||||
VSRL_IMM(ushr, ushr, 8, S, H, X)
|
||||
VSLL(sshl, sshl, 2, I, S, D)
|
||||
VSLL(sshl, sshl, 4, I, S, X)
|
||||
VSRA(negr, sshl, 2, I, S, D)
|
||||
VSRA(negr, sshl, 4, I, S, X)
|
||||
VSRL(negr, ushl, 2, I, S, D)
|
||||
VSRL(negr, ushl, 4, I, S, X)
|
||||
VSLL_IMM(shl, shl, 2, I, S, D)
|
||||
VSLL_IMM(shl, shl, 4, I, S, X)
|
||||
VSRA_IMM(sshr, sshr, 2, I, S, D)
|
||||
VSRA_IMM(sshr, sshr, 4, I, S, X)
|
||||
VSRL_IMM(ushr, ushr, 2, I, S, D)
|
||||
VSRL_IMM(ushr, ushr, 4, I, S, X)
|
||||
VSLL(sshl, sshl, 2, L, D, X)
|
||||
VSRA(negr, sshl, 2, L, D, X)
|
||||
VSRL(negr, ushl, 2, L, D, X)
|
||||
VSLL_IMM(shl, shl, 2, L, D, X)
|
||||
VSRA_IMM(sshr, sshr, 2, L, D, X)
|
||||
VSRL_IMM(ushr, ushr, 2, L, D, X)
|
||||
VSRAA_IMM(ssra, ssra, 8, B, B, D)
|
||||
VSRAA_IMM(ssra, ssra, 16, B, B, X)
|
||||
VSRAA_IMM(ssra, ssra, 4, S, H, D)
|
||||
VSRAA_IMM(ssra, ssra, 8, S, H, X)
|
||||
VSRAA_IMM(ssra, ssra, 2, I, S, D)
|
||||
VSRAA_IMM(ssra, ssra, 4, I, S, X)
|
||||
VSRAA_IMM(ssra, ssra, 2, L, D, X)
|
||||
VSRLA_IMM(usra, usra, 8, B, B, D)
|
||||
VSRLA_IMM(usra, usra, 16, B, B, X)
|
||||
VSRLA_IMM(usra, usra, 4, S, H, D)
|
||||
VSRLA_IMM(usra, usra, 8, S, H, X)
|
||||
VSRLA_IMM(usra, usra, 2, I, S, D)
|
||||
VSRLA_IMM(usra, usra, 4, I, S, X)
|
||||
VSRLA_IMM(usra, usra, 2, L, D, X)
|
||||
dnl
|
||||
define(`VMINMAX', `
|
||||
instruct v$1$3`'ifelse($5, S, F, D)`'(vec$6 dst, vec$6 src1, vec$6 src2)
|
||||
%{
|
||||
predicate(n->as_Vector()->length() == $3 && n->bottom_type()->is_vect()->element_basic_type() == T_`'ifelse($5, S, FLOAT, DOUBLE));
|
||||
match(Set dst ($2V src1 src2));
|
||||
ins_cost(INSN_COST);
|
||||
format %{ "f$1 $dst,$src1,$src2\t# vector ($3$4)" %}
|
||||
ins_encode %{
|
||||
__ f$1(as_FloatRegister($dst$$reg), __ T$3$5,
|
||||
as_FloatRegister($src1$$reg),
|
||||
as_FloatRegister($src2$$reg));
|
||||
%}
|
||||
ins_pipe(vdop_fp`'ifelse($6, D, 64, 128));
|
||||
%}')dnl
|
||||
dnl $1 $2 $3 $4 $5 $6
|
||||
VMINMAX(max, Max, 2, F, S, D)
|
||||
VMINMAX(max, Max, 4, S, S, X)
|
||||
VMINMAX(max, Max, 2, D, D, X)
|
||||
VMINMAX(min, Min, 2, F, S, D)
|
||||
VMINMAX(min, Min, 4, S, S, X)
|
||||
VMINMAX(min, Min, 2, D, D, X)
|
||||
|
||||
instruct vround2D_reg(vecX dst, vecX src, immI rmode) %{
|
||||
predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_DOUBLE);
|
||||
match(Set dst (RoundDoubleModeV src rmode));
|
||||
format %{ "frint $dst, $src, $rmode" %}
|
||||
ins_encode %{
|
||||
switch ($rmode$$constant) {
|
||||
case RoundDoubleModeNode::rmode_rint:
|
||||
__ frintn(as_FloatRegister($dst$$reg), __ T2D,
|
||||
as_FloatRegister($src$$reg));
|
||||
break;
|
||||
case RoundDoubleModeNode::rmode_floor:
|
||||
__ frintm(as_FloatRegister($dst$$reg), __ T2D,
|
||||
as_FloatRegister($src$$reg));
|
||||
break;
|
||||
case RoundDoubleModeNode::rmode_ceil:
|
||||
__ frintp(as_FloatRegister($dst$$reg), __ T2D,
|
||||
as_FloatRegister($src$$reg));
|
||||
break;
|
||||
}
|
||||
%}
|
||||
ins_pipe(vdop_fp128);
|
||||
%}
|
||||
dnl
|
||||
define(`VPOPCOUNT', `
|
||||
instruct vpopcount$1$2`'(vec$5 dst, vec$5 src) %{
|
||||
predicate(UsePopCountInstruction && n->as_Vector()->length() == $1);
|
||||
match(Set dst (PopCountVI src));
|
||||
format %{
|
||||
"cnt $dst, $src\t# vector ($3B)\n\t"
|
||||
"uaddlp $dst, $dst\t# vector ($3B)\n\t"
|
||||
"uaddlp $dst, $dst\t# vector ($4H)"
|
||||
%}
|
||||
ins_encode %{
|
||||
__ cnt(as_FloatRegister($dst$$reg), __ T$3B,
|
||||
as_FloatRegister($src$$reg));
|
||||
__ uaddlp(as_FloatRegister($dst$$reg), __ T$3B,
|
||||
as_FloatRegister($dst$$reg));
|
||||
__ uaddlp(as_FloatRegister($dst$$reg), __ T$4H,
|
||||
as_FloatRegister($dst$$reg));
|
||||
%}
|
||||
ins_pipe(pipe_class_default);
|
||||
%}')dnl
|
||||
dnl $1 $2 $3 $4 $5
|
||||
VPOPCOUNT(4, I, 16, 8, X)
|
||||
VPOPCOUNT(2, I, 8, 4, D)
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user