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8331732: [PPC64] Unify and optimize code which converts != 0 to 1

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Reviewed-by: mdoerr, amitkumar
This commit is contained in:
Suchismith Roy 2024-07-01 08:07:42 +00:00 committed by Martin Doerr
parent 53242cdf9e
commit c7e9ebb4cf
7 changed files with 43 additions and 21 deletions
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7
src/hotspot/cpu/ppc/assembler_ppc.hpp
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@ -1,6 +1,6 @@
/*
* Copyright (c) 2002, 2023, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2012, 2023 SAP SE. All rights reserved.
* Copyright (c) 2002, 2024, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2012, 2024 SAP SE. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -350,6 +350,7 @@ class Assembler : public AbstractAssembler {
SETBC_OPCODE = (31u << OPCODE_SHIFT | 384u << 1),
SETNBC_OPCODE = (31u << OPCODE_SHIFT | 448u << 1),
SETBCR_OPCODE = (31u << OPCODE_SHIFT | 416u << 1),
// condition register logic instructions
CRAND_OPCODE = (19u << OPCODE_SHIFT | 257u << 1),
@ -1780,6 +1781,8 @@ class Assembler : public AbstractAssembler {
inline void setbc( Register d, ConditionRegister cr, Condition cc);
inline void setnbc(Register d, int biint);
inline void setnbc(Register d, ConditionRegister cr, Condition cc);
inline void setbcr(Register d, int biint);
inline void setbcr(Register d, ConditionRegister cr, Condition cc);
// Special purpose registers
// Exception Register

9
src/hotspot/cpu/ppc/assembler_ppc.inline.hpp
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@ -1,6 +1,6 @@
/*
* Copyright (c) 2002, 2023, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2012, 2020 SAP SE. All rights reserved.
* Copyright (c) 2002, 2024, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2012, 2024 SAP SE. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -419,6 +419,11 @@ inline void Assembler::setnbc(Register d, int biint)
inline void Assembler::setnbc(Register d, ConditionRegister cr, Condition cc) {
setnbc(d, bi0(cr, cc));
}
inline void Assembler::setbcr(Register d, int biint)
{ emit_int32(SETBCR_OPCODE | rt(d) | bi(biint)); }
inline void Assembler::setbcr(Register d, ConditionRegister cr, Condition cc) {
setbcr(d, bi0(cr, cc));
}
// Special purpose registers
// Exception Register

9
src/hotspot/cpu/ppc/macroAssembler_ppc.cpp
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@ -2383,10 +2383,7 @@ void MacroAssembler::verify_secondary_supers_table(Register r_sub_klass,
addi(r_array_base, r_array_base, Array<Klass*>::base_offset_in_bytes());
// convert !=0 to 1
neg(R0, result);
orr(result, result, R0);
srdi(result, result, 63);
normalize_bool(result, R0, true);
const Register linear_result = r_array_index; // reuse
li(linear_result, 1);
cmpdi(CCR0, r_array_length, 0);
@ -2395,9 +2392,7 @@ void MacroAssembler::verify_secondary_supers_table(Register r_sub_klass,
bind(failure);
// convert !=0 to 1
neg(R0, linear_result);
orr(linear_result, linear_result, R0);
srdi(linear_result, linear_result, 63);
normalize_bool(linear_result, R0, true);
cmpd(CCR0, result, linear_result);
beq(CCR0, passed);

2
src/hotspot/cpu/ppc/macroAssembler_ppc.hpp
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@ -178,6 +178,8 @@ class MacroAssembler: public Assembler {
void inline set_cmp3(Register dst);
// set dst to (treat_unordered_like_less ? -1 : +1)
void inline set_cmpu3(Register dst, bool treat_unordered_like_less);
// Branch-free implementation to convert !=0 to 1.
void inline normalize_bool(Register dst, Register temp = R0, bool is_64bit = false);
inline void pd_patch_instruction(address branch, address target, const char* file, int line);
NOT_PRODUCT(static void pd_print_patched_instruction(address branch);)

27
src/hotspot/cpu/ppc/macroAssembler_ppc.inline.hpp
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@ -1,6 +1,6 @@
/*
* Copyright (c) 2002, 2023, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2012, 2021 SAP SE. All rights reserved.
* Copyright (c) 2002, 2024, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2012, 2024 SAP SE. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -264,6 +264,29 @@ inline void MacroAssembler::set_cmpu3(Register dst, bool treat_unordered_like_le
set_cmp3(dst);
}
// Branch-free implementation to convert !=0 to 1
// Set register dst to 1 if dst is non-zero. Uses setbcr instruction on Power10.
inline void MacroAssembler::normalize_bool(Register dst, Register temp, bool is_64bit) {
if (VM_Version::has_brw()) {
if (is_64bit) {
cmpdi(CCR0, dst, 0);
} else {
cmpwi(CCR0, dst, 0);
}
setbcr(dst, CCR0, Assembler::equal);
} else {
assert_different_registers(temp, dst);
neg(temp, dst);
orr(temp, dst, temp);
if (is_64bit) {
srdi(dst, temp, 63);
} else {
srwi(dst, temp, 31);
}
}
}
// Convenience bc_far versions
inline void MacroAssembler::blt_far(ConditionRegister crx, Label& L, int optimize) { MacroAssembler::bc_far(bcondCRbiIs1, bi0(crx, less), L, optimize); }
inline void MacroAssembler::bgt_far(ConditionRegister crx, Label& L, int optimize) { MacroAssembler::bc_far(bcondCRbiIs1, bi0(crx, greater), L, optimize); }

6
src/hotspot/cpu/ppc/sharedRuntime_ppc.cpp
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@ -2472,11 +2472,7 @@ nmethod *SharedRuntime::generate_native_wrapper(MacroAssembler *masm,
case T_ARRAY: break;
case T_BOOLEAN: { // 0 -> false(0); !0 -> true(1)
Label skip_modify;
__ cmpwi(CCR0, R3_RET, 0);
__ beq(CCR0, skip_modify);
__ li(R3_RET, 1);
__ bind(skip_modify);
__ normalize_bool(R3_RET);
break;
}
case T_BYTE: { // sign extension

4
src/hotspot/cpu/ppc/templateInterpreterGenerator_ppc.cpp
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@ -372,9 +372,7 @@ address TemplateInterpreterGenerator::generate_result_handler_for(BasicType type
switch (type) {
case T_BOOLEAN:
// convert !=0 to 1
__ neg(R0, R3_RET);
__ orr(R0, R3_RET, R0);
__ srwi(R3_RET, R0, 31);
__ normalize_bool(R3_RET);
break;
case T_BYTE:
// sign extend 8 bits