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Add __volatile__ to all __asm__ and make consistent indenting

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This commit is contained in:
Bruce Momjian 2001-01-19 03:58:35 +00:00
parent d7810023c5
commit cef28fd943
1 changed files with 69 additions and 64 deletions
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133
src/include/storage/s_lock.h
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@ -9,7 +9,7 @@
* *
* *
* IDENTIFICATION * IDENTIFICATION
* $Header: /cvsroot/pgsql/src/include/storage/s_lock.h,v 1.79 2001/01/19 02:58:59 momjian Exp $ * $Header: /cvsroot/pgsql/src/include/storage/s_lock.h,v 1.80 2001/01/19 03:58:35 momjian Exp $
* *
*------------------------------------------------------------------------- *-------------------------------------------------------------------------
*/ */
@ -100,9 +100,9 @@ extern void s_lock_sleep(unsigned spins, int microsec,
*/ */
/* /*
* Standard __asm__ format: * Standard _asm format:
* *
* __asm__( * __asm__ __volatile__(
* "command;" * "command;"
* "command;" * "command;"
* "command;" * "command;"
@ -120,11 +120,11 @@ tas(volatile slock_t *lock)
{ {
register slock_t _res = 1; register slock_t _res = 1;
__asm__( __asm__ __volatile__(
"lock;" "lock;"
"xchgb %0,%1;" "xchgb %0,%1;"
: "=q"(_res), "=m"(*lock) : "=q"(_res), "=m"(*lock)
: "0"(_res)); : "0"(_res));
return (int) _res; return (int) _res;
} }
@ -139,11 +139,11 @@ tas(volatile slock_t *lock)
{ {
long int ret; long int ret;
__asm__ __volatile__( __asm__ __volatile__(
"xchg4 %0=%1,%2;" "xchg4 %0=%1,%2;"
: "=r"(ret), "=m"(*lock) : "=r"(ret), "=m"(*lock)
: "r"(1), "1"(*lock) : "r"(1), "1"(*lock)
: "memory"); : "memory");
return (int) ret; return (int) ret;
} }
@ -159,10 +159,10 @@ tas(volatile slock_t *lock)
{ {
register slock_t _res = 1; register slock_t _res = 1;
__asm__( __asm__ __volatile__(
"swpb %0, %0, [%3];" "swpb %0, %0, [%3];"
: "=r"(_res), "=m"(*lock) : "=r"(_res), "=m"(*lock)
: "0"(_res), "r"(lock)); : "0"(_res), "r"(lock));
return (int) _res; return (int) _res;
} }
@ -179,15 +179,15 @@ tas(volatile slock_t *lock)
{ {
int _res; int _res;
__asm__ __volatile( __asm__ __volatile__(
"la 1,1;" "la 1,1;"
"l 2,%2;" "l 2,%2;"
"slr 0,0;" "slr 0,0;"
"cs 0,1,0(2);" "cs 0,1,0(2);"
"lr %1,0;" "lr %1,0;"
: "=m"(lock), "=d"(_res) : "=m"(lock), "=d"(_res)
: "m"(lock) : "m"(lock)
: "0", "1", "2"); : "0", "1", "2");
return (_res); return (_res);
} }
@ -203,10 +203,10 @@ tas(volatile slock_t *lock)
{ {
register slock_t _res = 1; register slock_t _res = 1;
__asm__( __asm__ __volatile__(
"ldstub [%2], %0;" "ldstub [%2], %0;"
: "=r"(_res), "=m"(*lock) : "=r"(_res), "=m"(*lock)
: "r"(lock)); : "r"(lock));
return (int) _res; return (int) _res;
} }
@ -221,12 +221,12 @@ tas(volatile slock_t *lock)
{ {
register int rv; register int rv;
__asm__ __volatile__( __asm__ __volatile__(
"tas %1;" "tas %1;"
"sne %0;" "sne %0;"
: "=d"(rv), "=m"(*lock) : "=d"(rv), "=m"(*lock)
: "1"(*lock) : "1"(*lock)
: "cc"); : "cc");
return rv; return rv;
} }
@ -248,14 +248,14 @@ tas(volatile slock_t *lock)
{ {
register _res; register _res;
__asm__( __asm__ __volatile__(
"movl $1, r0;" "movl $1, r0;"
"bbssi $0, (%1), 1f;" "bbssi $0, (%1), 1f;"
"clrl r0;" "clrl r0;"
"1: movl r0, %0;" "1: movl r0, %0;"
: "=r"(_res) : "=r"(_res)
: "r"(lock) : "r"(lock)
: "r0"); : "r0");
return (int) _res; return (int) _res;
} }
@ -270,10 +270,10 @@ tas(volatile slock_t *lock)
{ {
register _res; register _res;
__asm__( __asm__ __volatile__(
"sbitb 0, %0;" "sbitb 0, %0;"
"sfsd %1;" "sfsd %1;"
: "=m"(*lock), "=r"(_res)); : "=m"(*lock), "=r"(_res));
return (int) _res; return (int) _res;
} }
@ -326,28 +326,33 @@ tas(volatile slock_t *s_lock)
#if defined(__GNUC__) #if defined(__GNUC__)
#define TAS(lock) tas(lock) #define TAS(lock) tas(lock)
#define S_UNLOCK(lock) do { __asm__ volatile ("mb"); *(lock) = 0; } while (0) #define S_UNLOCK(lock) \
do \
{\
__asm__ __volatile__ ("mb"); \
*(lock) = 0; \
} while (0)
static __inline__ int static __inline__ int
tas(volatile slock_t *lock) tas(volatile slock_t *lock)
{ {
register slock_t _res; register slock_t _res;
__asm__ volatile( __asm__ __volatile__(
"ldq $0, %0;" "ldq $0, %0;"
"bne $0, 2f;" "bne $0, 2f;"
"ldq_l %1, %0;" "ldq_l %1, %0;"
"bne %1, 2f;" "bne %1, 2f;"
"mov 1, $0;" "mov 1, $0;"
"stq_c $0, %0;" "stq_c $0, %0;"
"beq $0, 2f;" "beq $0, 2f;"
"mb;" "mb;"
"br 3f;" "br 3f;"
"2: mov 1, %1;" "2: mov 1, %1;"
"3:" "3:"
: "=m"(*lock), "=r"(_res) : "=m"(*lock), "=r"(_res)
: :
: "0"); : "0");
return (int) _res; return (int) _res;
} }